1*4882a593Smuzhiyun* Marvell Armada 380/XP Buffer Manager driver (BM) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: should be "marvell,armada-380-neta-bm". 6*4882a593Smuzhiyun- reg: address and length of the register set for the device. 7*4882a593Smuzhiyun- clocks: a pointer to the reference clock for this device. 8*4882a593Smuzhiyun- internal-mem: a phandle to BM internal SRAM definition. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunOptional properties (port): 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained 13*4882a593Smuzhiyun in DRAM. Can be set for each pool (id 0 : 3) separately. The value has 14*4882a593Smuzhiyun to be chosen between 128 and 16352 and it also has to be aligned to 32. 15*4882a593Smuzhiyun Otherwise the driver would adjust a given number or choose default if 16*4882a593Smuzhiyun not set. 17*4882a593Smuzhiyun- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer 18*4882a593Smuzhiyun pointers' pool (id 0 : 3). It will be taken into consideration only when pool 19*4882a593Smuzhiyun type is 'short'. For 'long' ones it would be overridden by port's MTU. 20*4882a593Smuzhiyun If not set a driver will choose a default value. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunIn order to see how to hook the BM to a given ethernet port, please 23*4882a593Smuzhiyunrefer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- main node: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunbm: bm@c8000 { 30*4882a593Smuzhiyun compatible = "marvell,armada-380-neta-bm"; 31*4882a593Smuzhiyun reg = <0xc8000 0xac>; 32*4882a593Smuzhiyun clocks = <&gateclk 13>; 33*4882a593Smuzhiyun internal-mem = <&bm_bppi>; 34*4882a593Smuzhiyun pool2,capacity = <4096>; 35*4882a593Smuzhiyun pool1,pkt-size = <512>; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun- internal SRAM node: 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunbm_bppi: bm-bppi { 41*4882a593Smuzhiyun compatible = "mmio-sram"; 42*4882a593Smuzhiyun reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 43*4882a593Smuzhiyun ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <1>; 46*4882a593Smuzhiyun clocks = <&gateclk 13>; 47*4882a593Smuzhiyun}; 48