1*4882a593SmuzhiyunMarvell Prestera Switch Chip bindings 2*4882a593Smuzhiyun------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: must be "marvell,prestera" and one of the following 6*4882a593Smuzhiyun "marvell,prestera-98dx3236", 7*4882a593Smuzhiyun "marvell,prestera-98dx3336", 8*4882a593Smuzhiyun "marvell,prestera-98dx4251", 9*4882a593Smuzhiyun- reg: address and length of the register set for the device. 10*4882a593Smuzhiyun- interrupts: interrupt for the device 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun- dfx: phandle reference to the "DFX Server" node 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunswitch { 18*4882a593Smuzhiyun compatible = "simple-bus"; 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <1>; 21*4882a593Smuzhiyun ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun packet-processor@0 { 24*4882a593Smuzhiyun compatible = "marvell,prestera-98dx3236", "marvell,prestera"; 25*4882a593Smuzhiyun reg = <0 0x4000000>; 26*4882a593Smuzhiyun interrupts = <33>, <34>, <35>; 27*4882a593Smuzhiyun dfx = <&dfx>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunDFX Server bindings 32*4882a593Smuzhiyun------------------- 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunRequired properties: 35*4882a593Smuzhiyun- compatible: must be "marvell,dfx-server", "simple-bus" 36*4882a593Smuzhiyun- ranges: describes the address mapping of a memory-mapped bus. 37*4882a593Smuzhiyun- reg: address and length of the register set for the device. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunExample: 40*4882a593Smuzhiyun 41*4882a593Smuzhiyundfx-server { 42*4882a593Smuzhiyun compatible = "marvell,dfx-server", "simple-bus"; 43*4882a593Smuzhiyun #address-cells = <1>; 44*4882a593Smuzhiyun #size-cells = <1>; 45*4882a593Smuzhiyun ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; 46*4882a593Smuzhiyun reg = <MBUS_ID(0x08, 0x00) 0 0x100000>; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunMarvell Prestera SwitchDev bindings 50*4882a593Smuzhiyun----------------------------------- 51*4882a593SmuzhiyunOptional properties: 52*4882a593Smuzhiyun- compatible: must be "marvell,prestera" 53*4882a593Smuzhiyun- base-mac-provider: describes handle to node which provides base mac address, 54*4882a593Smuzhiyun might be a static base mac address or nvme cell provider. 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunExample: 57*4882a593Smuzhiyun 58*4882a593Smuzhiyuneeprom_mac_addr: eeprom-mac-addr { 59*4882a593Smuzhiyun compatible = "eeprom,mac-addr-cell"; 60*4882a593Smuzhiyun status = "okay"; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun nvmem = <&eeprom_at24>; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunprestera { 66*4882a593Smuzhiyun compatible = "marvell,prestera"; 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun base-mac-provider = <&eeprom_mac_addr>; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunThe current implementation of Prestera Switchdev PCI interface driver requires 73*4882a593Smuzhiyunthat BAR2 is assigned to 0xf6000000 as base address from the PCI IO range: 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&cp0_pcie0 { 76*4882a593Smuzhiyun ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000 77*4882a593Smuzhiyun 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000 78*4882a593Smuzhiyun 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>; 79*4882a593Smuzhiyun phys = <&cp0_comphy0 0>; 80*4882a593Smuzhiyun status = "okay"; 81*4882a593Smuzhiyun}; 82