1*4882a593SmuzhiyunThis document describes the device tree bindings associated with the 2*4882a593Smuzhiyunkeystone network coprocessor(NetCP) driver support. 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe network coprocessor (NetCP) is a hardware accelerator that processes 5*4882a593SmuzhiyunEthernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet 6*4882a593Smuzhiyunswitch sub-module to send and receive packets. NetCP also includes a packet 7*4882a593Smuzhiyunaccelerator (PA) module to perform packet classification operations such as 8*4882a593Smuzhiyunheader matching, and packet modification operations such as checksum 9*4882a593Smuzhiyungeneration. NetCP can also optionally include a Security Accelerator (SA) 10*4882a593Smuzhiyuncapable of performing IPSec operations on ingress/egress packets. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunKeystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which 13*4882a593Smuzhiyunincludes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates 14*4882a593Smuzhiyunper Ethernet port. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunKeystone NetCP driver has a plug-in module architecture where each of the NetCP 17*4882a593Smuzhiyunsub-modules exist as a loadable kernel module which plug in to the netcp core. 18*4882a593SmuzhiyunThese sub-modules are represented as "netcp-devices" in the dts bindings. It is 19*4882a593Smuzhiyunmandatory to have the ethernet switch sub-module for the ethernet interface to 20*4882a593Smuzhiyunbe operational. Any other sub-module like the PA is optional. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunNetCP Ethernet SubSystem Layout: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun----------------------------- 25*4882a593Smuzhiyun NetCP subsystem(10G or 1G) 26*4882a593Smuzhiyun----------------------------- 27*4882a593Smuzhiyun | 28*4882a593Smuzhiyun |-> NetCP Devices -> | 29*4882a593Smuzhiyun | |-> GBE/XGBE Switch 30*4882a593Smuzhiyun | | 31*4882a593Smuzhiyun | |-> Packet Accelerator 32*4882a593Smuzhiyun | | 33*4882a593Smuzhiyun | |-> Security Accelerator 34*4882a593Smuzhiyun | 35*4882a593Smuzhiyun | 36*4882a593Smuzhiyun | 37*4882a593Smuzhiyun |-> NetCP Interfaces -> | 38*4882a593Smuzhiyun |-> Ethernet Port 0 39*4882a593Smuzhiyun | 40*4882a593Smuzhiyun |-> Ethernet Port 1 41*4882a593Smuzhiyun | 42*4882a593Smuzhiyun |-> Ethernet Port 2 43*4882a593Smuzhiyun | 44*4882a593Smuzhiyun |-> Ethernet Port 3 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunNetCP subsystem properties: 48*4882a593SmuzhiyunRequired properties: 49*4882a593Smuzhiyun- compatible: Should be "ti,netcp-1.0" 50*4882a593Smuzhiyun- clocks: phandle to the reference clocks for the subsystem. 51*4882a593Smuzhiyun- dma-id: Navigator packet dma instance id. 52*4882a593Smuzhiyun- ranges: address range of NetCP (includes, Ethernet SS, PA and SA) 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunOptional properties: 55*4882a593Smuzhiyun- reg: register location and the size for the following register 56*4882a593Smuzhiyun regions in the specified order. 57*4882a593Smuzhiyun - Efuse MAC address register 58*4882a593Smuzhiyun- dma-coherent: Present if dma operations are coherent 59*4882a593Smuzhiyun- big-endian: Keystone devices can be operated in a mode where the DSP is in 60*4882a593Smuzhiyun the big endian mode. In such cases enable this option. This 61*4882a593Smuzhiyun option should also be enabled if the ARM is operated in 62*4882a593Smuzhiyun big endian mode with the DSP in little endian. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunNetCP device properties: Device specification for NetCP sub-modules. 65*4882a593Smuzhiyun1Gb/10Gb (gbe/xgbe) ethernet switch sub-module specifications. 66*4882a593SmuzhiyunRequired properties: 67*4882a593Smuzhiyun- label: Must be "netcp-gbe" for 1Gb & "netcp-xgbe" for 10Gb. 68*4882a593Smuzhiyun- compatible: Must be one of below:- 69*4882a593Smuzhiyun "ti,netcp-gbe" for 1GbE on NetCP 1.4 70*4882a593Smuzhiyun "ti,netcp-gbe-5" for 1GbE N NetCP 1.5 (N=5) 71*4882a593Smuzhiyun "ti,netcp-gbe-9" for 1GbE N NetCP 1.5 (N=9) 72*4882a593Smuzhiyun "ti,netcp-gbe-2" for 1GbE N NetCP 1.5 (N=2) 73*4882a593Smuzhiyun "ti,netcp-xgbe" for 10 GbE 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun- reg: register location and the size for the following register 76*4882a593Smuzhiyun regions in the specified order. 77*4882a593Smuzhiyun - switch subsystem registers 78*4882a593Smuzhiyun - sgmii port3/4 module registers (only for NetCP 1.4) 79*4882a593Smuzhiyun - switch module registers 80*4882a593Smuzhiyun - serdes registers (only for 10G) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun NetCP 1.4 ethss, here is the order 83*4882a593Smuzhiyun index #0 - switch subsystem registers 84*4882a593Smuzhiyun index #1 - sgmii port3/4 module registers 85*4882a593Smuzhiyun index #2 - switch module registers 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun NetCP 1.5 ethss 9 port, 5 port and 2 port 88*4882a593Smuzhiyun index #0 - switch subsystem registers 89*4882a593Smuzhiyun index #1 - switch module registers 90*4882a593Smuzhiyun index #2 - serdes registers 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun- tx-channel: the navigator packet dma channel name for tx. 93*4882a593Smuzhiyun- tx-queue: the navigator queue number associated with the tx dma channel. 94*4882a593Smuzhiyun- interfaces: specification for each of the switch port to be registered as a 95*4882a593Smuzhiyun network interface in the stack. 96*4882a593Smuzhiyun-- slave-port: Switch port number, 0 based numbering. 97*4882a593Smuzhiyun-- link-interface: type of link interface, supported options are 98*4882a593Smuzhiyun - mac<->mac auto negotiate mode: 0 99*4882a593Smuzhiyun - mac<->phy mode: 1 100*4882a593Smuzhiyun - mac<->mac forced mode: 2 101*4882a593Smuzhiyun - mac<->fiber mode: 3 102*4882a593Smuzhiyun - mac<->phy mode with no mdio: 4 103*4882a593Smuzhiyun - 10Gb mac<->phy mode : 10 104*4882a593Smuzhiyun - 10Gb mac<->mac forced mode : 11 105*4882a593Smuzhiyun----phy-handle: phandle to PHY device 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun- cpts: sub-node time synchronization (CPTS) submodule configuration 108*4882a593Smuzhiyun-- clocks: CPTS reference clock. Should point on cpts-refclk-mux clock. 109*4882a593Smuzhiyun-- clock-names: should be "cpts" 110*4882a593Smuzhiyun-- cpts-refclk-mux: multiplexer clock definition sub-node for CPTS reference (RFTCLK) clock 111*4882a593Smuzhiyun--- #clock-cells: should be 0 112*4882a593Smuzhiyun--- clocks: list of CPTS reference (RFTCLK) clock's parents as defined in Data manual 113*4882a593Smuzhiyun--- ti,mux-tbl: array of multiplexer indexes as defined in Data manual 114*4882a593Smuzhiyun--- assigned-clocks: should point on cpts-refclk-mux clock 115*4882a593Smuzhiyun--- assigned-clock-parents: should point on required RFTCLK clock parent to be selected 116*4882a593Smuzhiyun-- cpts_clock_mult: (optional) Numerator to convert input clock ticks 117*4882a593Smuzhiyun into nanoseconds 118*4882a593Smuzhiyun-- cpts_clock_shift: (optional) Denominator to convert input clock ticks into 119*4882a593Smuzhiyun nanoseconds. 120*4882a593Smuzhiyun Mult and shift will be calculated basing on CPTS 121*4882a593Smuzhiyun rftclk frequency if both cpts_clock_shift and 122*4882a593Smuzhiyun cpts_clock_mult properties are not provided. 123*4882a593Smuzhiyun 124*4882a593SmuzhiyunOptional properties: 125*4882a593Smuzhiyun- enable-ale: NetCP driver keeps the address learning feature in the ethernet 126*4882a593Smuzhiyun switch module disabled. This attribute is to enable the address 127*4882a593Smuzhiyun learning. 128*4882a593Smuzhiyun- secondary-slave-ports: specification for each of the switch port not be 129*4882a593Smuzhiyun registered as a network interface. NetCP driver 130*4882a593Smuzhiyun will only initialize these ports and attach PHY 131*4882a593Smuzhiyun driver to them if needed. 132*4882a593Smuzhiyun 133*4882a593SmuzhiyunNetCP interface properties: Interface specification for NetCP sub-modules. 134*4882a593SmuzhiyunRequired properties: 135*4882a593Smuzhiyun- rx-channel: the navigator packet dma channel name for rx. 136*4882a593Smuzhiyun- rx-queue: the navigator queue number associated with rx dma channel. 137*4882a593Smuzhiyun- rx-pool: specifies the number of descriptors to be used & the region-id 138*4882a593Smuzhiyun for creating the rx descriptor pool. 139*4882a593Smuzhiyun- tx-pool: specifies the number of descriptors to be used & the region-id 140*4882a593Smuzhiyun for creating the tx descriptor pool. 141*4882a593Smuzhiyun- rx-queue-depth: number of descriptors in each of the free descriptor 142*4882a593Smuzhiyun queue (FDQ) for the pktdma Rx flow. There can be at 143*4882a593Smuzhiyun present a maximum of 4 queues per Rx flow. 144*4882a593Smuzhiyun- rx-buffer-size: the buffer size for each of the Rx flow FDQ. 145*4882a593Smuzhiyun- tx-completion-queue: the navigator queue number where the descriptors are 146*4882a593Smuzhiyun recycled after Tx DMA completion. 147*4882a593Smuzhiyun 148*4882a593SmuzhiyunOptional properties: 149*4882a593Smuzhiyun- efuse-mac: If this is 1, then the MAC address for the interface is 150*4882a593Smuzhiyun obtained from the device efuse mac address register. 151*4882a593Smuzhiyun If this is 2, the two DWORDs occupied by the MAC address 152*4882a593Smuzhiyun are swapped. The netcp driver will swap the two DWORDs 153*4882a593Smuzhiyun back to the proper order when this property is set to 2 154*4882a593Smuzhiyun when it obtains the mac address from efuse. 155*4882a593Smuzhiyun- "netcp-device label": phandle to the device specification for each of NetCP 156*4882a593Smuzhiyun sub-module attached to this interface. 157*4882a593Smuzhiyun 158*4882a593SmuzhiyunThe MAC address will be determined using the optional properties defined in 159*4882a593Smuzhiyunethernet.txt and only if efuse-mac is set to 0. If all of the optional MAC 160*4882a593Smuzhiyunaddress properties are not present, then the driver will use a random MAC 161*4882a593Smuzhiyunaddress. 162*4882a593Smuzhiyun 163*4882a593SmuzhiyunExample binding: 164*4882a593Smuzhiyun 165*4882a593Smuzhiyunnetcp: netcp@2000000 { 166*4882a593Smuzhiyun reg = <0x2620110 0x8>; 167*4882a593Smuzhiyun reg-names = "efuse"; 168*4882a593Smuzhiyun compatible = "ti,netcp-1.0"; 169*4882a593Smuzhiyun #address-cells = <1>; 170*4882a593Smuzhiyun #size-cells = <1>; 171*4882a593Smuzhiyun ranges = <0 0x2000000 0xfffff>; 172*4882a593Smuzhiyun clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; 173*4882a593Smuzhiyun dma-coherent; 174*4882a593Smuzhiyun /* big-endian; */ 175*4882a593Smuzhiyun dma-id = <0>; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun netcp-devices { 178*4882a593Smuzhiyun #address-cells = <1>; 179*4882a593Smuzhiyun #size-cells = <1>; 180*4882a593Smuzhiyun ranges; 181*4882a593Smuzhiyun gbe@90000 { 182*4882a593Smuzhiyun label = "netcp-gbe"; 183*4882a593Smuzhiyun reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; 184*4882a593Smuzhiyun /* enable-ale; */ 185*4882a593Smuzhiyun tx-queue = <648>; 186*4882a593Smuzhiyun tx-channel = <8>; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun cpts { 189*4882a593Smuzhiyun clocks = <&cpts_refclk_mux>; 190*4882a593Smuzhiyun clock-names = "cpts"; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun cpts_refclk_mux: cpts-refclk-mux { 193*4882a593Smuzhiyun #clock-cells = <0>; 194*4882a593Smuzhiyun clocks = <&chipclk12>, <&chipclk13>, 195*4882a593Smuzhiyun <&timi0>, <&timi1>, 196*4882a593Smuzhiyun <&tsipclka>, <&tsrefclk>, 197*4882a593Smuzhiyun <&tsipclkb>; 198*4882a593Smuzhiyun ti,mux-tbl = <0x0>, <0x1>, <0x2>, 199*4882a593Smuzhiyun <0x3>, <0x4>, <0x8>, <0xC>; 200*4882a593Smuzhiyun assigned-clocks = <&cpts_refclk_mux>; 201*4882a593Smuzhiyun assigned-clock-parents = <&chipclk12>; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun interfaces { 206*4882a593Smuzhiyun gbe0: interface-0 { 207*4882a593Smuzhiyun slave-port = <0>; 208*4882a593Smuzhiyun link-interface = <4>; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun gbe1: interface-1 { 211*4882a593Smuzhiyun slave-port = <1>; 212*4882a593Smuzhiyun link-interface = <4>; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun secondary-slave-ports { 217*4882a593Smuzhiyun port-2 { 218*4882a593Smuzhiyun slave-port = <2>; 219*4882a593Smuzhiyun link-interface = <2>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun port-3 { 222*4882a593Smuzhiyun slave-port = <3>; 223*4882a593Smuzhiyun link-interface = <2>; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun netcp-interfaces { 230*4882a593Smuzhiyun interface-0 { 231*4882a593Smuzhiyun rx-channel = <22>; 232*4882a593Smuzhiyun rx-pool = <1024 12>; 233*4882a593Smuzhiyun tx-pool = <1024 12>; 234*4882a593Smuzhiyun rx-queue-depth = <128 128 0 0>; 235*4882a593Smuzhiyun rx-buffer-size = <1518 4096 0 0>; 236*4882a593Smuzhiyun rx-queue = <8704>; 237*4882a593Smuzhiyun tx-completion-queue = <8706>; 238*4882a593Smuzhiyun efuse-mac = <1>; 239*4882a593Smuzhiyun netcp-gbe = <&gbe0>; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun interface-1 { 243*4882a593Smuzhiyun rx-channel = <23>; 244*4882a593Smuzhiyun rx-pool = <1024 12>; 245*4882a593Smuzhiyun tx-pool = <1024 12>; 246*4882a593Smuzhiyun rx-queue-depth = <128 128 0 0>; 247*4882a593Smuzhiyun rx-buffer-size = <1518 4096 0 0>; 248*4882a593Smuzhiyun rx-queue = <8705>; 249*4882a593Smuzhiyun tx-completion-queue = <8707>; 250*4882a593Smuzhiyun efuse-mac = <0>; 251*4882a593Smuzhiyun local-mac-address = [02 18 31 7e 3e 6f]; 252*4882a593Smuzhiyun netcp-gbe = <&gbe1>; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593SmuzhiyunCPTS board configuration - select external CPTS RFTCLK: 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun&tsrefclk{ 260*4882a593Smuzhiyun clock-frequency = <500000000>; 261*4882a593Smuzhiyun}; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun&cpts_refclk_mux { 264*4882a593Smuzhiyun assigned-clock-parents = <&tsrefclk>; 265*4882a593Smuzhiyun}; 266