1*4882a593Smuzhiyun* IPQ806x DWMAC Ethernet controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe device inherits all the properties of the dwmac/stmmac devices 4*4882a593Smuzhiyundescribed in the file net/stmmac.txt with the following changes. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" 9*4882a593Smuzhiyun and any applicable more detailed version number 10*4882a593Smuzhiyun described in net/stmmac.txt 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- qcom,nss-common: should contain a phandle to a syscon device mapping the 13*4882a593Smuzhiyun nss-common registers. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the 16*4882a593Smuzhiyun qsgmii-csr registers. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun gmac: ethernet@37000000 { 21*4882a593Smuzhiyun device_type = "network"; 22*4882a593Smuzhiyun compatible = "qcom,ipq806x-gmac"; 23*4882a593Smuzhiyun reg = <0x37000000 0x200000>; 24*4882a593Smuzhiyun interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 25*4882a593Smuzhiyun interrupt-names = "macirq"; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun qcom,nss-common = <&nss_common>; 28*4882a593Smuzhiyun qcom,qsgmii-csr = <&qsgmii_csr>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks = <&gcc GMAC_CORE1_CLK>; 31*4882a593Smuzhiyun clock-names = "stmmaceth"; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun resets = <&gcc GMAC_CORE1_RESET>; 34*4882a593Smuzhiyun reset-names = "stmmaceth"; 35*4882a593Smuzhiyun }; 36