1*4882a593SmuzhiyunVitesse VSC73xx Switches 2*4882a593Smuzhiyun======================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis defines device tree bindings for the Vitesse VSC73xx switch chips. 5*4882a593SmuzhiyunThe Vitesse company has been acquired by Microsemi and Microsemi has 6*4882a593Smuzhiyunbeen acquired Microchip but retains this vendor branding. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunThe currently supported switch chips are: 9*4882a593SmuzhiyunVitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 10*4882a593SmuzhiyunVitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 11*4882a593SmuzhiyunVitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 12*4882a593SmuzhiyunVitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThis switch could have two different management interface. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunIf SPI interface is used, the device tree node is an SPI device so it must 17*4882a593Smuzhiyunreside inside a SPI bus device tree node, see spi/spi-bus.txt 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunWhen the chip is connected to a parallel memory bus and work in memory-mapped 20*4882a593SmuzhiyunI/O mode, a platform device is used to represent the vsc73xx. In this case it 21*4882a593Smuzhiyunmust reside inside a platform bus device tree node. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunRequired properties: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- compatible: must be exactly one of: 26*4882a593Smuzhiyun "vitesse,vsc7385" 27*4882a593Smuzhiyun "vitesse,vsc7388" 28*4882a593Smuzhiyun "vitesse,vsc7395" 29*4882a593Smuzhiyun "vitesse,vsc7398" 30*4882a593Smuzhiyun- gpio-controller: indicates that this switch is also a GPIO controller, 31*4882a593Smuzhiyun see gpio/gpio.txt 32*4882a593Smuzhiyun- #gpio-cells: this must be set to <2> and indicates that we are a twocell 33*4882a593Smuzhiyun GPIO controller, see gpio/gpio.txt 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunOptional properties: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- reset-gpios: a handle to a GPIO line that can issue reset of the chip. 38*4882a593Smuzhiyun It should be tagged as active low. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunRequired subnodes: 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunSee net/dsa/dsa.txt for a list of additional required and optional properties 43*4882a593Smuzhiyunand subnodes of DSA switches. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunExamples: 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunSPI: 48*4882a593Smuzhiyunswitch@0 { 49*4882a593Smuzhiyun compatible = "vitesse,vsc7395"; 50*4882a593Smuzhiyun reg = <0>; 51*4882a593Smuzhiyun /* Specified for 2.5 MHz or below */ 52*4882a593Smuzhiyun spi-max-frequency = <2500000>; 53*4882a593Smuzhiyun gpio-controller; 54*4882a593Smuzhiyun #gpio-cells = <2>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ports { 57*4882a593Smuzhiyun #address-cells = <1>; 58*4882a593Smuzhiyun #size-cells = <0>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun port@0 { 61*4882a593Smuzhiyun reg = <0>; 62*4882a593Smuzhiyun label = "lan1"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun port@1 { 65*4882a593Smuzhiyun reg = <1>; 66*4882a593Smuzhiyun label = "lan2"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun port@2 { 69*4882a593Smuzhiyun reg = <2>; 70*4882a593Smuzhiyun label = "lan3"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun port@3 { 73*4882a593Smuzhiyun reg = <3>; 74*4882a593Smuzhiyun label = "lan4"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun vsc: port@6 { 77*4882a593Smuzhiyun reg = <6>; 78*4882a593Smuzhiyun label = "cpu"; 79*4882a593Smuzhiyun ethernet = <&gmac1>; 80*4882a593Smuzhiyun phy-mode = "rgmii"; 81*4882a593Smuzhiyun fixed-link { 82*4882a593Smuzhiyun speed = <1000>; 83*4882a593Smuzhiyun full-duplex; 84*4882a593Smuzhiyun pause; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593SmuzhiyunPlatform: 91*4882a593Smuzhiyunswitch@2,0 { 92*4882a593Smuzhiyun #address-cells = <1>; 93*4882a593Smuzhiyun #size-cells = <1>; 94*4882a593Smuzhiyun compatible = "vitesse,vsc7385"; 95*4882a593Smuzhiyun reg = <0x2 0x0 0x20000>; 96*4882a593Smuzhiyun reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun ports { 99*4882a593Smuzhiyun #address-cells = <1>; 100*4882a593Smuzhiyun #size-cells = <0>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun port@0 { 103*4882a593Smuzhiyun reg = <0>; 104*4882a593Smuzhiyun label = "lan1"; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun port@1 { 107*4882a593Smuzhiyun reg = <1>; 108*4882a593Smuzhiyun label = "lan2"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun port@2 { 111*4882a593Smuzhiyun reg = <2>; 112*4882a593Smuzhiyun label = "lan3"; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun port@3 { 115*4882a593Smuzhiyun reg = <3>; 116*4882a593Smuzhiyun label = "lan4"; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun vsc: port@6 { 119*4882a593Smuzhiyun reg = <6>; 120*4882a593Smuzhiyun label = "cpu"; 121*4882a593Smuzhiyun ethernet = <&enet0>; 122*4882a593Smuzhiyun phy-mode = "rgmii"; 123*4882a593Smuzhiyun fixed-link { 124*4882a593Smuzhiyun speed = <1000>; 125*4882a593Smuzhiyun full-duplex; 126*4882a593Smuzhiyun pause; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun}; 132