1*4882a593SmuzhiyunRealtek SMI-based Switches 2*4882a593Smuzhiyun========================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe SMI "Simple Management Interface" is a two-wire protocol using 5*4882a593Smuzhiyunbit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does 6*4882a593Smuzhiyunnot use the MDIO protocol. This binding defines how to specify the 7*4882a593SmuzhiyunSMI-based Realtek devices. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- compatible: must be exactly one of: 12*4882a593Smuzhiyun "realtek,rtl8366" 13*4882a593Smuzhiyun "realtek,rtl8366rb" (4+1 ports) 14*4882a593Smuzhiyun "realtek,rtl8366s" (4+1 ports) 15*4882a593Smuzhiyun "realtek,rtl8367" 16*4882a593Smuzhiyun "realtek,rtl8367b" 17*4882a593Smuzhiyun "realtek,rtl8368s" (8 port) 18*4882a593Smuzhiyun "realtek,rtl8369" 19*4882a593Smuzhiyun "realtek,rtl8370" (8 port) 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunRequired properties: 22*4882a593Smuzhiyun- mdc-gpios: GPIO line for the MDC clock line. 23*4882a593Smuzhiyun- mdio-gpios: GPIO line for the MDIO data line. 24*4882a593Smuzhiyun- reset-gpios: GPIO line for the reset signal. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunOptional properties: 27*4882a593Smuzhiyun- realtek,disable-leds: if the LED drivers are not used in the 28*4882a593Smuzhiyun hardware design this will disable them so they are not turned on 29*4882a593Smuzhiyun and wasting power. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunRequired subnodes: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- interrupt-controller 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun This defines an interrupt controller with an IRQ line (typically 36*4882a593Smuzhiyun a GPIO) that will demultiplex and handle the interrupt from the single 37*4882a593Smuzhiyun interrupt line coming out of one of the SMI-based chips. It most 38*4882a593Smuzhiyun importantly provides link up/down interrupts to the PHY blocks inside 39*4882a593Smuzhiyun the ASIC. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunRequired properties of interrupt-controller: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun- interrupt: parent interrupt, see interrupt-controller/interrupts.txt 44*4882a593Smuzhiyun- interrupt-controller: see interrupt-controller/interrupts.txt 45*4882a593Smuzhiyun- #address-cells: should be <0> 46*4882a593Smuzhiyun- #interrupt-cells: should be <1> 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun- mdio 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun This defines the internal MDIO bus of the SMI device, mostly for the 51*4882a593Smuzhiyun purpose of being able to hook the interrupts to the right PHY and 52*4882a593Smuzhiyun the right PHY to the corresponding port. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunRequired properties of mdio: 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun- compatible: should be set to "realtek,smi-mdio" for all SMI devices 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunSee net/mdio.txt for additional MDIO bus properties. 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunSee net/dsa/dsa.txt for a list of additional required and optional properties 61*4882a593Smuzhiyunand subnodes of DSA switches. 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunExamples: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunswitch { 66*4882a593Smuzhiyun compatible = "realtek,rtl8366rb"; 67*4882a593Smuzhiyun /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ 68*4882a593Smuzhiyun mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; 69*4882a593Smuzhiyun mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; 70*4882a593Smuzhiyun reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun switch_intc: interrupt-controller { 73*4882a593Smuzhiyun /* GPIO 15 provides the interrupt */ 74*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 75*4882a593Smuzhiyun interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 76*4882a593Smuzhiyun interrupt-controller; 77*4882a593Smuzhiyun #address-cells = <0>; 78*4882a593Smuzhiyun #interrupt-cells = <1>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun ports { 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun #size-cells = <0>; 84*4882a593Smuzhiyun reg = <0>; 85*4882a593Smuzhiyun port@0 { 86*4882a593Smuzhiyun reg = <0>; 87*4882a593Smuzhiyun label = "lan0"; 88*4882a593Smuzhiyun phy-handle = <&phy0>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun port@1 { 91*4882a593Smuzhiyun reg = <1>; 92*4882a593Smuzhiyun label = "lan1"; 93*4882a593Smuzhiyun phy-handle = <&phy1>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun port@2 { 96*4882a593Smuzhiyun reg = <2>; 97*4882a593Smuzhiyun label = "lan2"; 98*4882a593Smuzhiyun phy-handle = <&phy2>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun port@3 { 101*4882a593Smuzhiyun reg = <3>; 102*4882a593Smuzhiyun label = "lan3"; 103*4882a593Smuzhiyun phy-handle = <&phy3>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun port@4 { 106*4882a593Smuzhiyun reg = <4>; 107*4882a593Smuzhiyun label = "wan"; 108*4882a593Smuzhiyun phy-handle = <&phy4>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun port@5 { 111*4882a593Smuzhiyun reg = <5>; 112*4882a593Smuzhiyun label = "cpu"; 113*4882a593Smuzhiyun ethernet = <&gmac0>; 114*4882a593Smuzhiyun phy-mode = "rgmii"; 115*4882a593Smuzhiyun fixed-link { 116*4882a593Smuzhiyun speed = <1000>; 117*4882a593Smuzhiyun full-duplex; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun mdio { 123*4882a593Smuzhiyun compatible = "realtek,smi-mdio", "dsa-mdio"; 124*4882a593Smuzhiyun #address-cells = <1>; 125*4882a593Smuzhiyun #size-cells = <0>; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun phy0: phy@0 { 128*4882a593Smuzhiyun reg = <0>; 129*4882a593Smuzhiyun interrupt-parent = <&switch_intc>; 130*4882a593Smuzhiyun interrupts = <0>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun phy1: phy@1 { 133*4882a593Smuzhiyun reg = <1>; 134*4882a593Smuzhiyun interrupt-parent = <&switch_intc>; 135*4882a593Smuzhiyun interrupts = <1>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun phy2: phy@2 { 138*4882a593Smuzhiyun reg = <2>; 139*4882a593Smuzhiyun interrupt-parent = <&switch_intc>; 140*4882a593Smuzhiyun interrupts = <2>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun phy3: phy@3 { 143*4882a593Smuzhiyun reg = <3>; 144*4882a593Smuzhiyun interrupt-parent = <&switch_intc>; 145*4882a593Smuzhiyun interrupts = <3>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun phy4: phy@4 { 148*4882a593Smuzhiyun reg = <4>; 149*4882a593Smuzhiyun interrupt-parent = <&switch_intc>; 150*4882a593Smuzhiyun interrupts = <12>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun}; 154