1*4882a593Smuzhiyun* MIX Ethernet controller. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunProperties: 4*4882a593Smuzhiyun- compatible: "cavium,octeon-5750-mix" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX 7*4882a593Smuzhiyun devices. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- reg: The base addresses of four separate register banks. The first 10*4882a593Smuzhiyun bank contains the MIX registers. The second bank the corresponding 11*4882a593Smuzhiyun AGL registers. The third bank are the AGL registers shared by all 12*4882a593Smuzhiyun MIX devices present. The fourth bank is the AGL_PRT_CTL shared by 13*4882a593Smuzhiyun all MIX devices present. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- cell-index: A single cell specifying which portion of the shared 16*4882a593Smuzhiyun register banks corresponds to this MIX device. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- interrupts: Two interrupt specifiers. The first is the MIX 19*4882a593Smuzhiyun interrupt routing and the second the routing for the AGL interrupts. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- phy-handle: Optional, see ethernet.txt file in the same directory. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun ethernet@1070000100800 { 25*4882a593Smuzhiyun compatible = "cavium,octeon-5750-mix"; 26*4882a593Smuzhiyun reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ 27*4882a593Smuzhiyun <0x11800 0xE0000800 0x0 0x300>, /* AGL */ 28*4882a593Smuzhiyun <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ 29*4882a593Smuzhiyun <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ 30*4882a593Smuzhiyun cell-index = <1>; 31*4882a593Smuzhiyun interrupts = <1 18>, < 1 46>; 32*4882a593Smuzhiyun local-mac-address = [ 00 0f b7 10 63 54 ]; 33*4882a593Smuzhiyun phy-handle = <&phy1>; 34*4882a593Smuzhiyun }; 35