xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/cavium-mdio.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* System Management Interface (SMI) / MDIO
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunProperties:
4*4882a593Smuzhiyun- compatible: One of:
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun   "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
7*4882a593Smuzhiyun                       and cn6XXX SOCs.
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun   "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun- reg: The base address of the MDIO bus controller register bank.
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun- #address-cells: Must be <1>.
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun- #size-cells: Must be <0>.  MDIO addresses have no size component.
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunTypically an MDIO bus might have several children.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunExample:
20*4882a593Smuzhiyun	mdio@1180000001800 {
21*4882a593Smuzhiyun		compatible = "cavium,octeon-3860-mdio";
22*4882a593Smuzhiyun		#address-cells = <1>;
23*4882a593Smuzhiyun		#size-cells = <0>;
24*4882a593Smuzhiyun		reg = <0x11800 0x00001800 0x0 0x40>;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		ethernet-phy@0 {
27*4882a593Smuzhiyun			...
28*4882a593Smuzhiyun			reg = <0>;
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun* System Management Interface (SMI) / MDIO Nexus
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  Several mdio buses may be gathered as children of a single PCI
36*4882a593Smuzhiyun  device, this PCI device is the nexus of the buses.
37*4882a593Smuzhiyun
38*4882a593SmuzhiyunProperties:
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun- compatible: "cavium,thunder-8890-mdio-nexus";
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun- reg: The PCI device and function numbers of the nexus device.
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun- #address-cells: Must be <2>.
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun- #size-cells: Must be <2>.
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun- ranges: As needed for mapping of the MDIO bus device registers.
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun- assigned-addresses: As needed for mapping of the MDIO bus device registers.
51*4882a593Smuzhiyun
52*4882a593SmuzhiyunExample:
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun        mdio-nexus@1,3 {
55*4882a593Smuzhiyun                compatible = "cavium,thunder-8890-mdio-nexus";
56*4882a593Smuzhiyun                #address-cells = <2>;
57*4882a593Smuzhiyun                #size-cells = <2>;
58*4882a593Smuzhiyun                reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59*4882a593Smuzhiyun                assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60*4882a593Smuzhiyun                ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun                mdio0@87e0,05003800 {
63*4882a593Smuzhiyun                        compatible = "cavium,thunder-8890-mdio";
64*4882a593Smuzhiyun                        #address-cells = <1>;
65*4882a593Smuzhiyun                        #size-cells = <0>;
66*4882a593Smuzhiyun                        reg = <0x87e0 0x05003800 0x0 0x30>;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun                        ethernet-phy@0 {
69*4882a593Smuzhiyun                                ...
70*4882a593Smuzhiyun                                reg = <0>;
71*4882a593Smuzhiyun                        };
72*4882a593Smuzhiyun                };
73*4882a593Smuzhiyun                mdio0@87e0,05003880 {
74*4882a593Smuzhiyun                        compatible = "cavium,thunder-8890-mdio";
75*4882a593Smuzhiyun                        #address-cells = <1>;
76*4882a593Smuzhiyun                        #size-cells = <0>;
77*4882a593Smuzhiyun                        reg = <0x87e0 0x05003880 0x0 0x30>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun                        ethernet-phy@0 {
80*4882a593Smuzhiyun                                ...
81*4882a593Smuzhiyun                                reg = <0>;
82*4882a593Smuzhiyun                        };
83*4882a593Smuzhiyun                };
84*4882a593Smuzhiyun        };
85