1*4882a593SmuzhiyunRenesas R-Car CAN FD controller Device Tree Bindings 2*4882a593Smuzhiyun---------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: Must contain one or more of the following: 6*4882a593Smuzhiyun - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers. 7*4882a593Smuzhiyun - "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller. 8*4882a593Smuzhiyun - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller. 9*4882a593Smuzhiyun - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller. 10*4882a593Smuzhiyun - "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller. 11*4882a593Smuzhiyun - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller. 12*4882a593Smuzhiyun - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller. 13*4882a593Smuzhiyun - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller. 14*4882a593Smuzhiyun - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller. 15*4882a593Smuzhiyun - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller. 16*4882a593Smuzhiyun - "renesas,r8a77990-canfd" for R8A77990 (R-Car E3) compatible controller. 17*4882a593Smuzhiyun - "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun When compatible with the generic version, nodes must list the 20*4882a593Smuzhiyun SoC-specific version corresponding to the platform first, followed by the 21*4882a593Smuzhiyun family-specific and/or generic versions. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- reg: physical base address and size of the R-Car CAN FD register map. 24*4882a593Smuzhiyun- interrupts: interrupt specifiers for the Channel & Global interrupts 25*4882a593Smuzhiyun- clocks: phandles and clock specifiers for 3 clock inputs. 26*4882a593Smuzhiyun- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk". 27*4882a593Smuzhiyun- pinctrl-0: pin control group to be used for this controller. 28*4882a593Smuzhiyun- pinctrl-names: must be "default". 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunRequired child nodes: 31*4882a593SmuzhiyunThe controller supports two channels and each is represented as a child node. 32*4882a593SmuzhiyunThe name of the child nodes are "channel0" and "channel1" respectively. Each 33*4882a593Smuzhiyunchild node supports the "status" property only, which is used to 34*4882a593Smuzhiyunenable/disable the respective channel. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunRequired properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795, 37*4882a593SmuzhiyunR8A7796, R8A77965, R8A77990, and R8A77995: 38*4882a593SmuzhiyunIn the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN 39*4882a593Smuzhiyunand CAN FD controller at the same time. It needs to be scaled to maximum 40*4882a593Smuzhiyunfrequency if any of these controllers use it. This is done using the below 41*4882a593Smuzhiyunproperties: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun- assigned-clocks: phandle of canfd clock. 44*4882a593Smuzhiyun- assigned-clock-rates: maximum frequency of this clock. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunOptional property: 47*4882a593SmuzhiyunThe controller can operate in either CAN FD only mode (default) or 48*4882a593SmuzhiyunClassical CAN only mode. The mode is global to both the channels. In order to 49*4882a593Smuzhiyunenable the later, define the following optional property. 50*4882a593Smuzhiyun - renesas,no-can-fd: puts the controller in Classical CAN only mode. 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunExample 53*4882a593Smuzhiyun------- 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunSoC common .dtsi file: 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun canfd: can@e66c0000 { 58*4882a593Smuzhiyun compatible = "renesas,r8a7795-canfd", 59*4882a593Smuzhiyun "renesas,rcar-gen3-canfd"; 60*4882a593Smuzhiyun reg = <0 0xe66c0000 0 0x8000>; 61*4882a593Smuzhiyun interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 62*4882a593Smuzhiyun <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 63*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 914>, 64*4882a593Smuzhiyun <&cpg CPG_CORE R8A7795_CLK_CANFD>, 65*4882a593Smuzhiyun <&can_clk>; 66*4882a593Smuzhiyun clock-names = "fck", "canfd", "can_clk"; 67*4882a593Smuzhiyun assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 68*4882a593Smuzhiyun assigned-clock-rates = <40000000>; 69*4882a593Smuzhiyun power-domains = <&cpg>; 70*4882a593Smuzhiyun status = "disabled"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun channel0 { 73*4882a593Smuzhiyun status = "disabled"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun channel1 { 77*4882a593Smuzhiyun status = "disabled"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunBoard specific .dts file: 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunE.g. below enables Channel 1 alone in the board in Classical CAN only mode. 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&canfd { 86*4882a593Smuzhiyun pinctrl-0 = <&canfd1_pins>; 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun renesas,no-can-fd; 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun channel1 { 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95*4882a593Smuzhiyun 96*4882a593SmuzhiyunE.g. below enables Channel 0 alone in the board using External clock 97*4882a593Smuzhiyunas fCAN clock. 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&canfd { 100*4882a593Smuzhiyun pinctrl-0 = <&canfd0_pins &can_clk_pins>; 101*4882a593Smuzhiyun pinctrl-names = "default"; 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun channel0 { 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun}; 108