1*4882a593SmuzhiyunRenesas R-Car CAN controller Device Tree Bindings 2*4882a593Smuzhiyun------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC. 6*4882a593Smuzhiyun "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC. 7*4882a593Smuzhiyun "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC. 8*4882a593Smuzhiyun "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC. 9*4882a593Smuzhiyun "renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC. 10*4882a593Smuzhiyun "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC. 11*4882a593Smuzhiyun "renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC. 12*4882a593Smuzhiyun "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC. 13*4882a593Smuzhiyun "renesas,can-r8a774e1" if CAN controller is a part of R8A774E1 SoC. 14*4882a593Smuzhiyun "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC. 15*4882a593Smuzhiyun "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC. 16*4882a593Smuzhiyun "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC. 17*4882a593Smuzhiyun "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC. 18*4882a593Smuzhiyun "renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC. 19*4882a593Smuzhiyun "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC. 20*4882a593Smuzhiyun "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC. 21*4882a593Smuzhiyun "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC. 22*4882a593Smuzhiyun "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC. 23*4882a593Smuzhiyun "renesas,can-r8a77965" if CAN controller is a part of R8A77965 SoC. 24*4882a593Smuzhiyun "renesas,can-r8a77990" if CAN controller is a part of R8A77990 SoC. 25*4882a593Smuzhiyun "renesas,can-r8a77995" if CAN controller is a part of R8A77995 SoC. 26*4882a593Smuzhiyun "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device. 27*4882a593Smuzhiyun "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1 28*4882a593Smuzhiyun compatible device. 29*4882a593Smuzhiyun "renesas,rcar-gen3-can" for a generic R-Car Gen3 or RZ/G2 30*4882a593Smuzhiyun compatible device. 31*4882a593Smuzhiyun When compatible with the generic version, nodes must list the 32*4882a593Smuzhiyun SoC-specific version corresponding to the platform first 33*4882a593Smuzhiyun followed by the generic version. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun- reg: physical base address and size of the R-Car CAN register map. 36*4882a593Smuzhiyun- interrupts: interrupt specifier for the sole interrupt. 37*4882a593Smuzhiyun- clocks: phandles and clock specifiers for 3 CAN clock inputs. 38*4882a593Smuzhiyun- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk". 39*4882a593Smuzhiyun- pinctrl-0: pin control group to be used for this controller. 40*4882a593Smuzhiyun- pinctrl-names: must be "default". 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunRequired properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795, 43*4882a593SmuzhiyunR8A7796, R8A77965, R8A77990, and R8A77995: 44*4882a593SmuzhiyunFor the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can 45*4882a593Smuzhiyunbe used by both CAN and CAN FD controller at the same time. It needs to be 46*4882a593Smuzhiyunscaled to maximum frequency if any of these controllers use it. This is done 47*4882a593Smuzhiyunusing the below properties: 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun- assigned-clocks: phandle of clkp2(CANFD) clock. 50*4882a593Smuzhiyun- assigned-clock-rates: maximum frequency of this clock. 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunOptional properties: 53*4882a593Smuzhiyun- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are: 54*4882a593Smuzhiyun <0x0> (default) : Peripheral clock (clkp1) 55*4882a593Smuzhiyun <0x1> : Peripheral clock (clkp2) 56*4882a593Smuzhiyun <0x3> : External input clock 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunExample 59*4882a593Smuzhiyun------- 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunSoC common .dtsi file: 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun can0: can@e6e80000 { 64*4882a593Smuzhiyun compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; 65*4882a593Smuzhiyun reg = <0 0xe6e80000 0 0x1000>; 66*4882a593Smuzhiyun interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; 67*4882a593Smuzhiyun clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, 68*4882a593Smuzhiyun <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; 69*4882a593Smuzhiyun clock-names = "clkp1", "clkp2", "can_clk"; 70*4882a593Smuzhiyun status = "disabled"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunBoard specific .dts file: 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&can0 { 76*4882a593Smuzhiyun pinctrl-0 = <&can0_pins>; 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun}; 80