1*4882a593SmuzhiyunAPM X-Gene SoC MDIO node 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMDIO node is defined to describe on-chip MDIO controller. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi" 7*4882a593Smuzhiyun - #address-cells: Must be <1>. 8*4882a593Smuzhiyun - #size-cells: Must be <0>. 9*4882a593Smuzhiyun - reg: Address and length of the register set 10*4882a593Smuzhiyun - clocks: Reference to the clock entry 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunFor the phys on the mdio bus, there must be a node with the following fields: 13*4882a593Smuzhiyun - compatible: PHY identifier. Please refer ./phy.txt for the format. 14*4882a593Smuzhiyun - reg: The ID number for the phy. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun mdio: mdio@17020000 { 19*4882a593Smuzhiyun compatible = "apm,xgene-mdio-rgmii"; 20*4882a593Smuzhiyun #address-cells = <1>; 21*4882a593Smuzhiyun #size-cells = <0>; 22*4882a593Smuzhiyun reg = <0x0 0x17020000 0x0 0xd100>; 23*4882a593Smuzhiyun clocks = <&menetclk 0>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Board-specific peripheral configurations */ 27*4882a593Smuzhiyun &mdio { 28*4882a593Smuzhiyun menetphy: phy@3 { 29*4882a593Smuzhiyun reg = <0x3>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun sgenet0phy: phy@4 { 32*4882a593Smuzhiyun reg = <0x4>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun sgenet1phy: phy@5 { 35*4882a593Smuzhiyun reg = <0x5>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38