1*4882a593SmuzhiyunAPM X-Gene SoC Ethernet nodes 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunEthernet nodes are defined to describe on-chip ethernet interfaces in 4*4882a593SmuzhiyunAPM X-Gene SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties for all the ethernet interfaces: 7*4882a593Smuzhiyun- compatible: Should state binding information from the following list, 8*4882a593Smuzhiyun - "apm,xgene-enet": RGMII based 1G interface 9*4882a593Smuzhiyun - "apm,xgene1-sgenet": SGMII based 1G interface 10*4882a593Smuzhiyun - "apm,xgene1-xgenet": XFI based 10G interface 11*4882a593Smuzhiyun- reg: Address and length of the register set for the device. It contains the 12*4882a593Smuzhiyun information of registers in the same order as described by reg-names 13*4882a593Smuzhiyun- reg-names: Should contain the register set names 14*4882a593Smuzhiyun - "enet_csr": Ethernet control and status register address space 15*4882a593Smuzhiyun - "ring_csr": Descriptor ring control and status register address space 16*4882a593Smuzhiyun - "ring_cmd": Descriptor ring command register address space 17*4882a593Smuzhiyun- interrupts: Two interrupt specifiers can be specified. 18*4882a593Smuzhiyun - First is the Rx interrupt. This irq is mandatory. 19*4882a593Smuzhiyun - Second is the Tx completion interrupt. 20*4882a593Smuzhiyun This is supported only on SGMII based 1GbE and 10GbE interfaces. 21*4882a593Smuzhiyun- channel: Ethernet to CPU, start channel (prefetch buffer) number 22*4882a593Smuzhiyun - Must map to the first irq and irqs must be sequential 23*4882a593Smuzhiyun- port-id: Port number (0 or 1) 24*4882a593Smuzhiyun- clocks: Reference to the clock entry. 25*4882a593Smuzhiyun- local-mac-address: MAC address assigned to this device 26*4882a593Smuzhiyun- phy-connection-type: Interface type between ethernet device and PHY device 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunRequired properties for ethernet interfaces that have external PHY: 29*4882a593Smuzhiyun- phy-handle: Reference to a PHY node connected to this device 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun- mdio: Device tree subnode with the following required properties: 32*4882a593Smuzhiyun - compatible: Must be "apm,xgene-mdio". 33*4882a593Smuzhiyun - #address-cells: Must be <1>. 34*4882a593Smuzhiyun - #size-cells: Must be <0>. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun For the phy on the mdio bus, there must be a node with the following fields: 37*4882a593Smuzhiyun - compatible: PHY identifier. Please refer ./phy.txt for the format. 38*4882a593Smuzhiyun - reg: The ID number for the phy. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunOptional properties: 41*4882a593Smuzhiyun- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok". 42*4882a593Smuzhiyun- tx-delay: Delay value for RGMII bridge TX clock. 43*4882a593Smuzhiyun Valid values are between 0 to 7, that maps to 44*4882a593Smuzhiyun 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps 45*4882a593Smuzhiyun Default value is 4, which corresponds to 1611 ps 46*4882a593Smuzhiyun- rx-delay: Delay value for RGMII bridge RX clock. 47*4882a593Smuzhiyun Valid values are between 0 to 7, that maps to 48*4882a593Smuzhiyun 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps 49*4882a593Smuzhiyun Default value is 2, which corresponds to 899 ps 50*4882a593Smuzhiyun- rxlos-gpios: Input gpio from SFP+ module to indicate availability of 51*4882a593Smuzhiyun incoming signal. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunExample: 55*4882a593Smuzhiyun menetclk: menetclk { 56*4882a593Smuzhiyun compatible = "apm,xgene-device-clock"; 57*4882a593Smuzhiyun clock-output-names = "menetclk"; 58*4882a593Smuzhiyun status = "ok"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun menet: ethernet@17020000 { 62*4882a593Smuzhiyun compatible = "apm,xgene-enet"; 63*4882a593Smuzhiyun status = "disabled"; 64*4882a593Smuzhiyun reg = <0x0 0x17020000 0x0 0xd100>, 65*4882a593Smuzhiyun <0x0 0x17030000 0x0 0x400>, 66*4882a593Smuzhiyun <0x0 0x10000000 0x0 0x200>; 67*4882a593Smuzhiyun reg-names = "enet_csr", "ring_csr", "ring_cmd"; 68*4882a593Smuzhiyun interrupts = <0x0 0x3c 0x4>; 69*4882a593Smuzhiyun port-id = <0>; 70*4882a593Smuzhiyun clocks = <&menetclk 0>; 71*4882a593Smuzhiyun local-mac-address = [00 01 73 00 00 01]; 72*4882a593Smuzhiyun phy-connection-type = "rgmii"; 73*4882a593Smuzhiyun phy-handle = <&menetphy>; 74*4882a593Smuzhiyun mdio { 75*4882a593Smuzhiyun compatible = "apm,xgene-mdio"; 76*4882a593Smuzhiyun #address-cells = <1>; 77*4882a593Smuzhiyun #size-cells = <0>; 78*4882a593Smuzhiyun menetphy: menetphy@3 { 79*4882a593Smuzhiyun compatible = "ethernet-phy-id001c.c915"; 80*4882a593Smuzhiyun reg = <0x3>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun/* Board-specific peripheral configurations */ 87*4882a593Smuzhiyun&menet { 88*4882a593Smuzhiyun tx-delay = <4>; 89*4882a593Smuzhiyun rx-delay = <2>; 90*4882a593Smuzhiyun status = "ok"; 91*4882a593Smuzhiyun}; 92