1*4882a593Smuzhiyun* AMD 10GbE driver (amd-xgbe) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "amd,xgbe-seattle-v1a" 5*4882a593Smuzhiyun- reg: Address and length of the register sets for the device 6*4882a593Smuzhiyun - MAC registers 7*4882a593Smuzhiyun - PCS registers 8*4882a593Smuzhiyun - SerDes Rx/Tx registers 9*4882a593Smuzhiyun - SerDes integration registers (1/2) 10*4882a593Smuzhiyun - SerDes integration registers (2/2) 11*4882a593Smuzhiyun- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt 12*4882a593Smuzhiyun listed is required and is the general device interrupt. If the optional 13*4882a593Smuzhiyun amd,per-channel-interrupt property is specified, then one additional 14*4882a593Smuzhiyun interrupt for each DMA channel supported by the device should be specified. 15*4882a593Smuzhiyun The last interrupt listed should be the PCS auto-negotiation interrupt. 16*4882a593Smuzhiyun- clocks: 17*4882a593Smuzhiyun - DMA clock for the amd-xgbe device (used for calculating the 18*4882a593Smuzhiyun correct Rx interrupt watchdog timer value on a DMA channel 19*4882a593Smuzhiyun for coalescing) 20*4882a593Smuzhiyun - PTP clock for the amd-xgbe device 21*4882a593Smuzhiyun- clock-names: Should be the names of the clocks 22*4882a593Smuzhiyun - "dma_clk" for the DMA clock 23*4882a593Smuzhiyun - "ptp_clk" for the PTP clock 24*4882a593Smuzhiyun- phy-mode: See ethernet.txt file in the same directory 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunOptional properties: 27*4882a593Smuzhiyun- dma-coherent: Present if dma operations are coherent 28*4882a593Smuzhiyun- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate 29*4882a593Smuzhiyun a unique interrupt for each DMA channel - this requires an additional 30*4882a593Smuzhiyun interrupt be configured for each DMA channel 31*4882a593Smuzhiyun- amd,speed-set: Speed capabilities of the device 32*4882a593Smuzhiyun 0 - 1GbE and 10GbE (default) 33*4882a593Smuzhiyun 1 - 2.5GbE and 10GbE 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunThe MAC address will be determined using the optional properties defined in 36*4882a593Smuzhiyunethernet.txt. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunThe following optional properties are represented by an array with each 39*4882a593Smuzhiyunvalue corresponding to a particular speed. The first array value represents 40*4882a593Smuzhiyunthe setting for the 1GbE speed, the second value for the 2.5GbE speed and 41*4882a593Smuzhiyunthe third value for the 10GbE speed. All three values are required if the 42*4882a593Smuzhiyunproperty is used. 43*4882a593Smuzhiyun- amd,serdes-blwc: Baseline wandering correction enablement 44*4882a593Smuzhiyun 0 - Off 45*4882a593Smuzhiyun 1 - On 46*4882a593Smuzhiyun- amd,serdes-cdr-rate: CDR rate speed selection 47*4882a593Smuzhiyun- amd,serdes-pq-skew: PQ (data sampling) skew 48*4882a593Smuzhiyun- amd,serdes-tx-amp: TX amplitude boost 49*4882a593Smuzhiyun- amd,serdes-dfe-tap-config: DFE taps available to run 50*4882a593Smuzhiyun- amd,serdes-dfe-tap-enable: DFE taps to enable 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunExample: 53*4882a593Smuzhiyun xgbe@e0700000 { 54*4882a593Smuzhiyun compatible = "amd,xgbe-seattle-v1a"; 55*4882a593Smuzhiyun reg = <0 0xe0700000 0 0x80000>, 56*4882a593Smuzhiyun <0 0xe0780000 0 0x80000>, 57*4882a593Smuzhiyun <0 0xe1240800 0 0x00400>, 58*4882a593Smuzhiyun <0 0xe1250000 0 0x00060>, 59*4882a593Smuzhiyun <0 0xe1250080 0 0x00004>; 60*4882a593Smuzhiyun interrupt-parent = <&gic>; 61*4882a593Smuzhiyun interrupts = <0 325 4>, 62*4882a593Smuzhiyun <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, 63*4882a593Smuzhiyun <0 323 4>; 64*4882a593Smuzhiyun amd,per-channel-interrupt; 65*4882a593Smuzhiyun clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; 66*4882a593Smuzhiyun clock-names = "dma_clk", "ptp_clk"; 67*4882a593Smuzhiyun phy-mode = "xgmii"; 68*4882a593Smuzhiyun mac-address = [ 02 a1 a2 a3 a4 a5 ]; 69*4882a593Smuzhiyun amd,speed-set = <0>; 70*4882a593Smuzhiyun amd,serdes-blwc = <1>, <1>, <0>; 71*4882a593Smuzhiyun amd,serdes-cdr-rate = <2>, <2>, <7>; 72*4882a593Smuzhiyun amd,serdes-pq-skew = <10>, <10>, <30>; 73*4882a593Smuzhiyun amd,serdes-tx-amp = <15>, <15>, <10>; 74*4882a593Smuzhiyun amd,serdes-dfe-tap-config = <3>, <3>, <1>; 75*4882a593Smuzhiyun amd,serdes-dfe-tap-enable = <0>, <0>, <127>; 76*4882a593Smuzhiyun }; 77