1*4882a593Smuzhiyun* Andestech L2 cache Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe level-2 cache controller plays an important role in reducing memory latency 4*4882a593Smuzhiyunfor high performance systems, such as thoese designs with AndesCore processors. 5*4882a593SmuzhiyunLevel-2 cache controller in general enhances overall system performance 6*4882a593Smuzhiyunsignigicantly and the system power consumption might be reduced as well by 7*4882a593Smuzhiyunreducing DRAM accesses. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThis binding specifies what properties must be available in the device tree 10*4882a593Smuzhiyunrepresentation of an Andestech L2 cache controller. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun - compatible: 14*4882a593Smuzhiyun Usage: required 15*4882a593Smuzhiyun Value type: <string> 16*4882a593Smuzhiyun Definition: "andestech,atl2c" 17*4882a593Smuzhiyun - reg : Physical base address and size of cache controller's memory mapped 18*4882a593Smuzhiyun - cache-unified : Specifies the cache is a unified cache. 19*4882a593Smuzhiyun - cache-level : Should be set to 2 for a level 2 cache. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun* Example 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun cache-controller@e0500000 { 24*4882a593Smuzhiyun compatible = "andestech,atl2c"; 25*4882a593Smuzhiyun reg = <0xe0500000 0x1000>; 26*4882a593Smuzhiyun cache-unified; 27*4882a593Smuzhiyun cache-level = <2>; 28*4882a593Smuzhiyun }; 29