1*4882a593SmuzhiyunBindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : Should be one of 5*4882a593Smuzhiyun * "adi,adgs1408" 6*4882a593Smuzhiyun * "adi,adgs1409" 7*4882a593Smuzhiyun* Standard mux-controller bindings as described in mux-controller.txt 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional properties for ADGS1408/1409: 10*4882a593Smuzhiyun- gpio-controller : if present, #gpio-cells is required. 11*4882a593Smuzhiyun- #gpio-cells : should be <2> 12*4882a593Smuzhiyun - First cell is the GPO line number, i.e. 0 to 3 13*4882a593Smuzhiyun for ADGS1408 and 0 to 4 for ADGS1409 14*4882a593Smuzhiyun - Second cell is used to specify active high (0) 15*4882a593Smuzhiyun or active low (1) 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- idle-state : if present, the state that the mux controller will have 19*4882a593Smuzhiyun when idle. The special state MUX_IDLE_AS_IS is the default and 20*4882a593Smuzhiyun MUX_IDLE_DISCONNECT is also supported. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunStates 0 through 7 correspond to signals S1 through S8 in the datasheet. 23*4882a593SmuzhiyunFor ADGS1409 only states 0 to 3 are available. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * One mux controller. 29*4882a593Smuzhiyun * Mux state set to idle as is (no idle-state declared) 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun &spi0 { 32*4882a593Smuzhiyun mux: mux-controller@0 { 33*4882a593Smuzhiyun compatible = "adi,adgs1408"; 34*4882a593Smuzhiyun reg = <0>; 35*4882a593Smuzhiyun spi-max-frequency = <1000000>; 36*4882a593Smuzhiyun #mux-control-cells = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun } 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun adc-mux { 41*4882a593Smuzhiyun compatible = "io-channel-mux"; 42*4882a593Smuzhiyun io-channels = <&adc 1>; 43*4882a593Smuzhiyun io-channel-names = "parent"; 44*4882a593Smuzhiyun mux-controls = <&mux>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun channels = "out_a0", "out_a1", "test0", "test1", 47*4882a593Smuzhiyun "out_b0", "out_b1", "testb0", "testb1"; 48*4882a593Smuzhiyun }; 49