1*4882a593SmuzhiyunBindings for Analog Devices ADG792A/G Triple 4:1 Multiplexers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "adi,adg792a" or "adi,adg792g" 5*4882a593Smuzhiyun- #mux-control-cells : <0> if parallel (the three muxes are bound together 6*4882a593Smuzhiyun with a single mux controller controlling all three muxes), or <1> if 7*4882a593Smuzhiyun not (one mux controller for each mux). 8*4882a593Smuzhiyun* Standard mux-controller bindings as described in mux-controller.txt 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunOptional properties for ADG792G: 11*4882a593Smuzhiyun- gpio-controller : if present, #gpio-cells below is required. 12*4882a593Smuzhiyun- #gpio-cells : should be <2> 13*4882a593Smuzhiyun - First cell is the GPO line number, i.e. 0 or 1 14*4882a593Smuzhiyun - Second cell is used to specify active high (0) 15*4882a593Smuzhiyun or active low (1) 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- idle-state : if present, array of states that the mux controllers will have 19*4882a593Smuzhiyun when idle. The special state MUX_IDLE_AS_IS is the default and 20*4882a593Smuzhiyun MUX_IDLE_DISCONNECT is also supported. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunStates 0 through 3 correspond to signals A through D in the datasheet. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Three independent mux controllers (of which one is used). 28*4882a593Smuzhiyun * Mux 0 is disconnected when idle, mux 1 idles in the previously 29*4882a593Smuzhiyun * selected state and mux 2 idles with signal B. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun &i2c0 { 32*4882a593Smuzhiyun mux: mux-controller@50 { 33*4882a593Smuzhiyun compatible = "adi,adg792a"; 34*4882a593Smuzhiyun reg = <0x50>; 35*4882a593Smuzhiyun #mux-control-cells = <1>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 1>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun adc-mux { 42*4882a593Smuzhiyun compatible = "io-channel-mux"; 43*4882a593Smuzhiyun io-channels = <&adc 0>; 44*4882a593Smuzhiyun io-channel-names = "parent"; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun mux-controls = <&mux 2>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun channels = "sync-1", "", "out"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * Three parallel muxes with one mux controller, useful e.g. if 54*4882a593Smuzhiyun * the adc is differential, thus needing two signals to be muxed 55*4882a593Smuzhiyun * simultaneously for correct operation. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun &i2c0 { 58*4882a593Smuzhiyun pmux: mux-controller@50 { 59*4882a593Smuzhiyun compatible = "adi,adg792a"; 60*4882a593Smuzhiyun reg = <0x50>; 61*4882a593Smuzhiyun #mux-control-cells = <0>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun idle-state = <1>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun diff-adc-mux { 68*4882a593Smuzhiyun compatible = "io-channel-mux"; 69*4882a593Smuzhiyun io-channels = <&adc 0>; 70*4882a593Smuzhiyun io-channel-names = "parent"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun mux-controls = <&pmux>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun channels = "sync-1", "", "out"; 75*4882a593Smuzhiyun }; 76