1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Christophe Kerello <christophe.kerello@st.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun enum: 15*4882a593Smuzhiyun - st,stm32mp15-fmc2 16*4882a593Smuzhiyun - st,stm32mp1-fmc2-nfc 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reg: 19*4882a593Smuzhiyun minItems: 6 20*4882a593Smuzhiyun maxItems: 7 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun interrupts: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun dmas: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - description: tx DMA channel 28*4882a593Smuzhiyun - description: rx DMA channel 29*4882a593Smuzhiyun - description: ecc DMA channel 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun dma-names: 32*4882a593Smuzhiyun items: 33*4882a593Smuzhiyun - const: tx 34*4882a593Smuzhiyun - const: rx 35*4882a593Smuzhiyun - const: ecc 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunpatternProperties: 38*4882a593Smuzhiyun "^nand@[a-f0-9]$": 39*4882a593Smuzhiyun type: object 40*4882a593Smuzhiyun properties: 41*4882a593Smuzhiyun nand-ecc-step-size: 42*4882a593Smuzhiyun const: 512 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun nand-ecc-strength: 45*4882a593Smuzhiyun enum: [1, 4, 8] 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunallOf: 48*4882a593Smuzhiyun - $ref: "nand-controller.yaml#" 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun - if: 51*4882a593Smuzhiyun properties: 52*4882a593Smuzhiyun compatible: 53*4882a593Smuzhiyun contains: 54*4882a593Smuzhiyun const: st,stm32mp15-fmc2 55*4882a593Smuzhiyun then: 56*4882a593Smuzhiyun properties: 57*4882a593Smuzhiyun reg: 58*4882a593Smuzhiyun items: 59*4882a593Smuzhiyun - description: Registers 60*4882a593Smuzhiyun - description: Chip select 0 data 61*4882a593Smuzhiyun - description: Chip select 0 command 62*4882a593Smuzhiyun - description: Chip select 0 address space 63*4882a593Smuzhiyun - description: Chip select 1 data 64*4882a593Smuzhiyun - description: Chip select 1 command 65*4882a593Smuzhiyun - description: Chip select 1 address space 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun clocks: 68*4882a593Smuzhiyun maxItems: 1 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun resets: 71*4882a593Smuzhiyun maxItems: 1 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun required: 74*4882a593Smuzhiyun - clocks 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun - if: 77*4882a593Smuzhiyun properties: 78*4882a593Smuzhiyun compatible: 79*4882a593Smuzhiyun contains: 80*4882a593Smuzhiyun const: st,stm32mp1-fmc2-nfc 81*4882a593Smuzhiyun then: 82*4882a593Smuzhiyun properties: 83*4882a593Smuzhiyun reg: 84*4882a593Smuzhiyun items: 85*4882a593Smuzhiyun - description: Chip select 0 data 86*4882a593Smuzhiyun - description: Chip select 0 command 87*4882a593Smuzhiyun - description: Chip select 0 address space 88*4882a593Smuzhiyun - description: Chip select 1 data 89*4882a593Smuzhiyun - description: Chip select 1 command 90*4882a593Smuzhiyun - description: Chip select 1 address space 91*4882a593Smuzhiyun 92*4882a593Smuzhiyunrequired: 93*4882a593Smuzhiyun - compatible 94*4882a593Smuzhiyun - reg 95*4882a593Smuzhiyun - interrupts 96*4882a593Smuzhiyun 97*4882a593SmuzhiyununevaluatedProperties: false 98*4882a593Smuzhiyun 99*4882a593Smuzhiyunexamples: 100*4882a593Smuzhiyun - | 101*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 102*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 103*4882a593Smuzhiyun #include <dt-bindings/reset/stm32mp1-resets.h> 104*4882a593Smuzhiyun nand-controller@58002000 { 105*4882a593Smuzhiyun compatible = "st,stm32mp15-fmc2"; 106*4882a593Smuzhiyun reg = <0x58002000 0x1000>, 107*4882a593Smuzhiyun <0x80000000 0x1000>, 108*4882a593Smuzhiyun <0x88010000 0x1000>, 109*4882a593Smuzhiyun <0x88020000 0x1000>, 110*4882a593Smuzhiyun <0x81000000 0x1000>, 111*4882a593Smuzhiyun <0x89010000 0x1000>, 112*4882a593Smuzhiyun <0x89020000 0x1000>; 113*4882a593Smuzhiyun interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 114*4882a593Smuzhiyun dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 115*4882a593Smuzhiyun <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 116*4882a593Smuzhiyun <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 117*4882a593Smuzhiyun dma-names = "tx", "rx", "ecc"; 118*4882a593Smuzhiyun clocks = <&rcc FMC_K>; 119*4882a593Smuzhiyun resets = <&rcc FMC_R>; 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <0>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun nand@0 { 124*4882a593Smuzhiyun reg = <0>; 125*4882a593Smuzhiyun nand-on-flash-bbt; 126*4882a593Smuzhiyun #address-cells = <1>; 127*4882a593Smuzhiyun #size-cells = <1>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun... 132