1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mtd/nand-controller.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NAND Chip and NAND Controller Generic Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Miquel Raynal <miquel.raynal@bootlin.com> 11*4882a593Smuzhiyun - Richard Weinberger <richard@nod.at> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun The NAND controller should be represented with its own DT node, and 15*4882a593Smuzhiyun all NAND chips attached to this controller should be defined as 16*4882a593Smuzhiyun children nodes of the NAND controller. This representation should be 17*4882a593Smuzhiyun enforced even for simple controllers supporting only one chip. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun The ECC strength and ECC step size properties define the user 20*4882a593Smuzhiyun desires in terms of correction capability of a controller. Together, 21*4882a593Smuzhiyun they request the ECC engine to correct {strength} bit errors per 22*4882a593Smuzhiyun {size} bytes. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun The interpretation of these parameters is implementation-defined, so 25*4882a593Smuzhiyun not all implementations must support all possible 26*4882a593Smuzhiyun combinations. However, implementations are encouraged to further 27*4882a593Smuzhiyun specify the value(s) they support. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunproperties: 30*4882a593Smuzhiyun $nodename: 31*4882a593Smuzhiyun pattern: "^nand-controller(@.*)?" 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun "#address-cells": 34*4882a593Smuzhiyun const: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun "#size-cells": 37*4882a593Smuzhiyun const: 0 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun ranges: true 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunpatternProperties: 42*4882a593Smuzhiyun "^nand@[a-f0-9]$": 43*4882a593Smuzhiyun type: object 44*4882a593Smuzhiyun properties: 45*4882a593Smuzhiyun reg: 46*4882a593Smuzhiyun description: 47*4882a593Smuzhiyun Contains the chip-select IDs. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun nand-ecc-mode: 50*4882a593Smuzhiyun description: 51*4882a593Smuzhiyun Desired ECC engine, either hardware (most of the time 52*4882a593Smuzhiyun embedded in the NAND controller) or software correction 53*4882a593Smuzhiyun (Linux will handle the calculations). soft_bch is deprecated 54*4882a593Smuzhiyun and should be replaced by soft and nand-ecc-algo. 55*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/string 56*4882a593Smuzhiyun enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die] 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun nand-ecc-engine: 59*4882a593Smuzhiyun allOf: 60*4882a593Smuzhiyun - $ref: /schemas/types.yaml#/definitions/phandle 61*4882a593Smuzhiyun description: | 62*4882a593Smuzhiyun A phandle on the hardware ECC engine if any. There are 63*4882a593Smuzhiyun basically three possibilities: 64*4882a593Smuzhiyun 1/ The ECC engine is part of the NAND controller, in this 65*4882a593Smuzhiyun case the phandle should reference the parent node. 66*4882a593Smuzhiyun 2/ The ECC engine is part of the NAND part (on-die), in this 67*4882a593Smuzhiyun case the phandle should reference the node itself. 68*4882a593Smuzhiyun 3/ The ECC engine is external, in this case the phandle should 69*4882a593Smuzhiyun reference the specific ECC engine node. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun nand-use-soft-ecc-engine: 72*4882a593Smuzhiyun type: boolean 73*4882a593Smuzhiyun description: Use a software ECC engine. 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun nand-no-ecc-engine: 76*4882a593Smuzhiyun type: boolean 77*4882a593Smuzhiyun description: Do not use any ECC correction. 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun nand-ecc-placement: 80*4882a593Smuzhiyun allOf: 81*4882a593Smuzhiyun - $ref: /schemas/types.yaml#/definitions/string 82*4882a593Smuzhiyun - enum: [ oob, interleaved ] 83*4882a593Smuzhiyun description: 84*4882a593Smuzhiyun Location of the ECC bytes. This location is unknown by default 85*4882a593Smuzhiyun but can be explicitly set to "oob", if all ECC bytes are 86*4882a593Smuzhiyun known to be stored in the OOB area, or "interleaved" if ECC 87*4882a593Smuzhiyun bytes will be interleaved with regular data in the main area. 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun nand-ecc-algo: 90*4882a593Smuzhiyun description: 91*4882a593Smuzhiyun Desired ECC algorithm. 92*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/string 93*4882a593Smuzhiyun enum: [hamming, bch, rs] 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun nand-bus-width: 96*4882a593Smuzhiyun description: 97*4882a593Smuzhiyun Bus width to the NAND chip 98*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 99*4882a593Smuzhiyun enum: [8, 16] 100*4882a593Smuzhiyun default: 8 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun nand-on-flash-bbt: 103*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/flag 104*4882a593Smuzhiyun description: 105*4882a593Smuzhiyun With this property, the OS will search the device for a Bad 106*4882a593Smuzhiyun Block Table (BBT). If not found, it will create one, reserve 107*4882a593Smuzhiyun a few blocks at the end of the device to store it and update 108*4882a593Smuzhiyun it as the device ages. Otherwise, the out-of-band area of a 109*4882a593Smuzhiyun few pages of all the blocks will be scanned at boot time to 110*4882a593Smuzhiyun find Bad Block Markers (BBM). These markers will help to 111*4882a593Smuzhiyun build a volatile BBT in RAM. 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun nand-ecc-strength: 114*4882a593Smuzhiyun description: 115*4882a593Smuzhiyun Maximum number of bits that can be corrected per ECC step. 116*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 117*4882a593Smuzhiyun minimum: 1 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun nand-ecc-step-size: 120*4882a593Smuzhiyun description: 121*4882a593Smuzhiyun Number of data bytes covered by a single ECC step. 122*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 123*4882a593Smuzhiyun minimum: 1 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun nand-ecc-maximize: 126*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/flag 127*4882a593Smuzhiyun description: 128*4882a593Smuzhiyun Whether or not the ECC strength should be maximized. The 129*4882a593Smuzhiyun maximum ECC strength is both controller and chip 130*4882a593Smuzhiyun dependent. The ECC engine has to select the ECC config 131*4882a593Smuzhiyun providing the best strength and taking the OOB area size 132*4882a593Smuzhiyun constraint into account. This is particularly useful when 133*4882a593Smuzhiyun only the in-band area is used by the upper layers, and you 134*4882a593Smuzhiyun want to make your NAND as reliable as possible. 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun nand-is-boot-medium: 137*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/flag 138*4882a593Smuzhiyun description: 139*4882a593Smuzhiyun Whether or not the NAND chip is a boot medium. Drivers might 140*4882a593Smuzhiyun use this information to select ECC algorithms supported by 141*4882a593Smuzhiyun the boot ROM or similar restrictions. 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun nand-rb: 144*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32-array 145*4882a593Smuzhiyun description: 146*4882a593Smuzhiyun Contains the native Ready/Busy IDs. 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun rb-gpios: 149*4882a593Smuzhiyun description: 150*4882a593Smuzhiyun Contains one or more GPIO descriptor (the numper of descriptor 151*4882a593Smuzhiyun depends on the number of R/B pins exposed by the flash) for the 152*4882a593Smuzhiyun Ready/Busy pins. Active state refers to the NAND ready state and 153*4882a593Smuzhiyun should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun required: 156*4882a593Smuzhiyun - reg 157*4882a593Smuzhiyun 158*4882a593Smuzhiyunrequired: 159*4882a593Smuzhiyun - "#address-cells" 160*4882a593Smuzhiyun - "#size-cells" 161*4882a593Smuzhiyun 162*4882a593SmuzhiyunadditionalProperties: true 163*4882a593Smuzhiyun 164*4882a593Smuzhiyunexamples: 165*4882a593Smuzhiyun - | 166*4882a593Smuzhiyun nand-controller { 167*4882a593Smuzhiyun #address-cells = <1>; 168*4882a593Smuzhiyun #size-cells = <0>; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* controller specific properties */ 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun nand@0 { 173*4882a593Smuzhiyun reg = <0>; 174*4882a593Smuzhiyun nand-ecc-mode = "soft"; 175*4882a593Smuzhiyun nand-ecc-algo = "bch"; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* NAND chip specific properties */ 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun }; 180