1*4882a593SmuzhiyunMacronix Raw NAND Controller Device Tree Bindings 2*4882a593Smuzhiyun------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: should be "mxic,multi-itfc-v009-nand-controller" 6*4882a593Smuzhiyun- reg: should contain 1 entry for the registers 7*4882a593Smuzhiyun- #address-cells: should be set to 1 8*4882a593Smuzhiyun- #size-cells: should be set to 0 9*4882a593Smuzhiyun- interrupts: interrupt line connected to this raw NAND controller 10*4882a593Smuzhiyun- clock-names: should contain "ps", "send" and "send_dly" 11*4882a593Smuzhiyun- clocks: should contain 3 phandles for the "ps", "send" and 12*4882a593Smuzhiyun "send_dly" clocks 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunChildren nodes: 15*4882a593Smuzhiyun- children nodes represent the available NAND chips. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunSee Documentation/devicetree/bindings/mtd/nand-controller.yaml 18*4882a593Smuzhiyunfor more details on generic bindings. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun nand: nand-controller@43c30000 { 23*4882a593Smuzhiyun compatible = "mxic,multi-itfc-v009-nand-controller"; 24*4882a593Smuzhiyun reg = <0x43c30000 0x10000>; 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>; 28*4882a593Smuzhiyun clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>; 29*4882a593Smuzhiyun clock-names = "send", "send_dly", "ps"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun nand@0 { 32*4882a593Smuzhiyun reg = <0>; 33*4882a593Smuzhiyun nand-ecc-mode = "soft"; 34*4882a593Smuzhiyun nand-ecc-algo = "bch"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37