1*4882a593SmuzhiyunCFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunFlash chips (Memory Technology Devices) are often used for solid state 4*4882a593Smuzhiyunfile systems on embedded devices. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun - compatible : should contain the specific model of mtd chip(s) 7*4882a593Smuzhiyun used, if known, followed by either "cfi-flash", "jedec-flash", 8*4882a593Smuzhiyun "mtd-ram" or "mtd-rom". 9*4882a593Smuzhiyun - reg : Address range(s) of the mtd chip(s) 10*4882a593Smuzhiyun It's possible to (optionally) define multiple "reg" tuples so that 11*4882a593Smuzhiyun non-identical chips can be described in one node. 12*4882a593Smuzhiyun - bank-width : Width (in bytes) of the bank. Equal to the 13*4882a593Smuzhiyun device width times the number of interleaved chips. 14*4882a593Smuzhiyun - device-width : (optional) Width of a single mtd chip. If 15*4882a593Smuzhiyun omitted, assumed to be equal to 'bank-width'. 16*4882a593Smuzhiyun - #address-cells, #size-cells : Must be present if the device has 17*4882a593Smuzhiyun sub-nodes representing partitions (see below). In this case 18*4882a593Smuzhiyun both #address-cells and #size-cells must be equal to 1. 19*4882a593Smuzhiyun - no-unaligned-direct-access: boolean to disable the default direct 20*4882a593Smuzhiyun mapping of the flash. 21*4882a593Smuzhiyun On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause 22*4882a593Smuzhiyun problems with JFFS2 usage, as the local bus (LPB) doesn't support 23*4882a593Smuzhiyun unaligned accesses as implemented in the JFFS2 code via memcpy(). 24*4882a593Smuzhiyun By defining "no-unaligned-direct-access", the flash will not be 25*4882a593Smuzhiyun exposed directly to the MTD users (e.g. JFFS2) any more. 26*4882a593Smuzhiyun - linux,mtd-name: allow to specify the mtd name for retro capability with 27*4882a593Smuzhiyun physmap-flash drivers as boot loader pass the mtd partition via the old 28*4882a593Smuzhiyun device name physmap-flash. 29*4882a593Smuzhiyun - use-advanced-sector-protection: boolean to enable support for the 30*4882a593Smuzhiyun advanced sector protection (Spansion: PPB - Persistent Protection 31*4882a593Smuzhiyun Bits) locking. 32*4882a593Smuzhiyun - addr-gpios : (optional) List of GPIO descriptors that will be used to 33*4882a593Smuzhiyun address the MSBs address lines. The order goes from LSB to MSB. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunFor JEDEC compatible devices, the following additional properties 36*4882a593Smuzhiyunare defined: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun - vendor-id : Contains the flash chip's vendor id (1 byte). 39*4882a593Smuzhiyun - device-id : Contains the flash chip's device id (1 byte). 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunFor ROM compatible devices (and ROM fallback from cfi-flash), the following 42*4882a593Smuzhiyunadditional (optional) property is defined: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun - erase-size : The chip's physical erase block size in bytes. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun The device tree may optionally contain endianness property. 47*4882a593Smuzhiyun little-endian or big-endian : It Represents the endianness that should be used 48*4882a593Smuzhiyun by the controller to properly read/write data 49*4882a593Smuzhiyun from/to the flash. If this property is missing, 50*4882a593Smuzhiyun the endianness is chosen by the system 51*4882a593Smuzhiyun (potentially based on extra configuration options). 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunThe device tree may optionally contain sub-nodes describing partitions of the 54*4882a593Smuzhiyunaddress space. See partition.txt for more detail. 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunExample: 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun flash@ff000000 { 59*4882a593Smuzhiyun compatible = "amd,am29lv128ml", "cfi-flash"; 60*4882a593Smuzhiyun reg = <ff000000 01000000>; 61*4882a593Smuzhiyun bank-width = <4>; 62*4882a593Smuzhiyun device-width = <1>; 63*4882a593Smuzhiyun #address-cells = <1>; 64*4882a593Smuzhiyun #size-cells = <1>; 65*4882a593Smuzhiyun fs@0 { 66*4882a593Smuzhiyun label = "fs"; 67*4882a593Smuzhiyun reg = <0 f80000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun firmware@f80000 { 70*4882a593Smuzhiyun label ="firmware"; 71*4882a593Smuzhiyun reg = <f80000 80000>; 72*4882a593Smuzhiyun read-only; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunHere an example with multiple "reg" tuples: 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun flash@f0000000,0 { 79*4882a593Smuzhiyun #address-cells = <1>; 80*4882a593Smuzhiyun #size-cells = <1>; 81*4882a593Smuzhiyun compatible = "intel,PC48F4400P0VB", "cfi-flash"; 82*4882a593Smuzhiyun reg = <0 0x00000000 0x02000000 83*4882a593Smuzhiyun 0 0x02000000 0x02000000>; 84*4882a593Smuzhiyun bank-width = <2>; 85*4882a593Smuzhiyun partition@0 { 86*4882a593Smuzhiyun label = "test-part1"; 87*4882a593Smuzhiyun reg = <0 0x04000000>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunAn example using SRAM: 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun sram@2,0 { 94*4882a593Smuzhiyun compatible = "samsung,k6f1616u6a", "mtd-ram"; 95*4882a593Smuzhiyun reg = <2 0 0x00200000>; 96*4882a593Smuzhiyun bank-width = <2>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593SmuzhiyunAn example using gpio-addrs 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun flash@20000000 { 102*4882a593Smuzhiyun #address-cells = <1>; 103*4882a593Smuzhiyun #size-cells = <1>; 104*4882a593Smuzhiyun compatible = "cfi-flash", "jedec-flash"; 105*4882a593Smuzhiyun reg = <0x20000000 0x02000000>; 106*4882a593Smuzhiyun ranges = <0 0x00000000 0x02000000 107*4882a593Smuzhiyun 1 0x02000000 0x02000000>; 108*4882a593Smuzhiyun bank-width = <2>; 109*4882a593Smuzhiyun addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 110*4882a593Smuzhiyun partition@0 { 111*4882a593Smuzhiyun label = "test-part1"; 112*4882a593Smuzhiyun reg = <0 0x04000000>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115