1*4882a593SmuzhiyunNXP LPC32xx SoC NAND MLC controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "nxp,lpc3220-mlc" 5*4882a593Smuzhiyun- reg: Address and size of the controller 6*4882a593Smuzhiyun- interrupts: The NAND interrupt specification 7*4882a593Smuzhiyun- gpios: GPIO specification for NAND write protect 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe following required properties are very controller specific. See the LPC32xx 10*4882a593SmuzhiyunUser Manual 7.5.14 MLC NAND Timing Register (the values here are specified in 11*4882a593SmuzhiyunHz, to make them independent of actual clock speed and to provide for good 12*4882a593Smuzhiyunaccuracy:) 13*4882a593Smuzhiyun- nxp,tcea_delay: TCEA_DELAY 14*4882a593Smuzhiyun- nxp,busy_delay: BUSY_DELAY 15*4882a593Smuzhiyun- nxp,nand_ta: NAND_TA 16*4882a593Smuzhiyun- nxp,rd_high: RD_HIGH 17*4882a593Smuzhiyun- nxp,rd_low: RD_LOW 18*4882a593Smuzhiyun- nxp,wr_high: WR_HIGH 19*4882a593Smuzhiyun- nxp,wr_low: WR_LOW 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional subnodes: 22*4882a593Smuzhiyun- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun mlc: flash@200a8000 { 27*4882a593Smuzhiyun compatible = "nxp,lpc3220-mlc"; 28*4882a593Smuzhiyun reg = <0x200A8000 0x11000>; 29*4882a593Smuzhiyun interrupts = <11 0>; 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <1>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun nxp,tcea-delay = <333333333>; 34*4882a593Smuzhiyun nxp,busy-delay = <10000000>; 35*4882a593Smuzhiyun nxp,nand-ta = <18181818>; 36*4882a593Smuzhiyun nxp,rd-high = <31250000>; 37*4882a593Smuzhiyun nxp,rd-low = <45454545>; 38*4882a593Smuzhiyun nxp,wr-high = <40000000>; 39*4882a593Smuzhiyun nxp,wr-low = <83333333>; 40*4882a593Smuzhiyun gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun mtd0@00000000 { 43*4882a593Smuzhiyun label = "boot"; 44*4882a593Smuzhiyun reg = <0x00000000 0x00064000>; 45*4882a593Smuzhiyun read-only; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun ... 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun }; 51