1*4882a593SmuzhiyunFreescale Localbus UPM programmed to work with NAND flash 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "fsl,upm-nand". 5*4882a593Smuzhiyun- reg : should specify localbus chip select and size used for the chip. 6*4882a593Smuzhiyun- fsl,upm-addr-offset : UPM pattern offset for the address latch. 7*4882a593Smuzhiyun- fsl,upm-cmd-offset : UPM pattern offset for the command latch. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional properties: 10*4882a593Smuzhiyun- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. 11*4882a593Smuzhiyun The corresponding address lines are used to select the chip. 12*4882a593Smuzhiyun- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins 13*4882a593Smuzhiyun (R/B#). For multi-chip devices, "n" GPIO definitions are required 14*4882a593Smuzhiyun according to the number of chips. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunDeprecated properties: 17*4882a593Smuzhiyun- fsl,upm-wait-flags : add chip-dependent short delays after running the 18*4882a593Smuzhiyun UPM pattern (0x1), after writing a data byte (0x2) or after 19*4882a593Smuzhiyun writing out a buffer (0x4). 20*4882a593Smuzhiyun- chip-delay : chip dependent delay for transferring data from array to 21*4882a593Smuzhiyun read registers (tR). Required if property "gpios" is not used 22*4882a593Smuzhiyun (R/B# pins not connected). 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunEach flash chip described may optionally contain additional sub-nodes 25*4882a593Smuzhiyundescribing partitions of the address space. See partition.txt for more 26*4882a593Smuzhiyundetail. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExamples: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunupm@1,0 { 31*4882a593Smuzhiyun compatible = "fsl,upm-nand"; 32*4882a593Smuzhiyun reg = <1 0 1>; 33*4882a593Smuzhiyun fsl,upm-addr-offset = <16>; 34*4882a593Smuzhiyun fsl,upm-cmd-offset = <8>; 35*4882a593Smuzhiyun gpios = <&qe_pio_e 18 0>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun flash { 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <1>; 40*4882a593Smuzhiyun compatible = "..."; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun partition@0 { 43*4882a593Smuzhiyun ... 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunupm@3,0 { 49*4882a593Smuzhiyun #address-cells = <0>; 50*4882a593Smuzhiyun #size-cells = <0>; 51*4882a593Smuzhiyun compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; 52*4882a593Smuzhiyun reg = <3 0x0 0x800>; 53*4882a593Smuzhiyun fsl,upm-addr-offset = <0x10>; 54*4882a593Smuzhiyun fsl,upm-cmd-offset = <0x08>; 55*4882a593Smuzhiyun /* Multi-chip NAND device */ 56*4882a593Smuzhiyun fsl,upm-addr-line-cs-offsets = <0x0 0x200>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun nand@0 { 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <1>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun partition@0 { 63*4882a593Smuzhiyun label = "fs"; 64*4882a593Smuzhiyun reg = <0x00000000 0x10000000>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun}; 68