1*4882a593Smuzhiyun* Cadence Quad SPI controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should be one of the following: 5*4882a593Smuzhiyun Generic default - "cdns,qspi-nor". 6*4882a593Smuzhiyun For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". 7*4882a593Smuzhiyun For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". 8*4882a593Smuzhiyun- reg : Contains two entries, each of which is a tuple consisting of a 9*4882a593Smuzhiyun physical address and length. The first entry is the address and 10*4882a593Smuzhiyun length of the controller register set. The second entry is the 11*4882a593Smuzhiyun address and length of the QSPI Controller data area. 12*4882a593Smuzhiyun- interrupts : Unit interrupt specifier for the controller interrupt. 13*4882a593Smuzhiyun- clocks : phandle to the Quad SPI clock. 14*4882a593Smuzhiyun- cdns,fifo-depth : Size of the data FIFO in words. 15*4882a593Smuzhiyun- cdns,fifo-width : Bus width of the data FIFO in bytes. 16*4882a593Smuzhiyun- cdns,trigger-address : 32-bit indirect AHB trigger address. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. 20*4882a593Smuzhiyun- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch 21*4882a593Smuzhiyun the read data rather than the QSPI clock. Make sure that QSPI return 22*4882a593Smuzhiyun clock is populated on the board before using this property. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional subnodes: 25*4882a593SmuzhiyunSubnodes of the Cadence Quad SPI controller are spi slave nodes with additional 26*4882a593Smuzhiyuncustom properties: 27*4882a593Smuzhiyun- cdns,read-delay : Delay for read capture logic, in clock cycles 28*4882a593Smuzhiyun- cdns,tshsl-ns : Delay in nanoseconds for the length that the master 29*4882a593Smuzhiyun mode chip select outputs are de-asserted between 30*4882a593Smuzhiyun transactions. 31*4882a593Smuzhiyun- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being 32*4882a593Smuzhiyun de-activated and the activation of another. 33*4882a593Smuzhiyun- cdns,tchsh-ns : Delay in nanoseconds between last bit of current 34*4882a593Smuzhiyun transaction and deasserting the device chip select 35*4882a593Smuzhiyun (qspi_n_ss_out). 36*4882a593Smuzhiyun- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low 37*4882a593Smuzhiyun and first bit transfer. 38*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 39*4882a593Smuzhiyun See ../reset/reset.txt for details. 40*4882a593Smuzhiyun- reset-names : Must include either "qspi" and/or "qspi-ocp". 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunExample: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun qspi: spi@ff705000 { 45*4882a593Smuzhiyun compatible = "cdns,qspi-nor"; 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <0>; 48*4882a593Smuzhiyun reg = <0xff705000 0x1000>, 49*4882a593Smuzhiyun <0xffa00000 0x1000>; 50*4882a593Smuzhiyun interrupts = <0 151 4>; 51*4882a593Smuzhiyun clocks = <&qspi_clk>; 52*4882a593Smuzhiyun cdns,is-decoded-cs; 53*4882a593Smuzhiyun cdns,fifo-depth = <128>; 54*4882a593Smuzhiyun cdns,fifo-width = <4>; 55*4882a593Smuzhiyun cdns,trigger-address = <0x00000000>; 56*4882a593Smuzhiyun resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; 57*4882a593Smuzhiyun reset-names = "qspi", "qspi-ocp"; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun flash0: n25q00@0 { 60*4882a593Smuzhiyun ... 61*4882a593Smuzhiyun cdns,read-delay = <4>; 62*4882a593Smuzhiyun cdns,tshsl-ns = <50>; 63*4882a593Smuzhiyun cdns,tsd2d-ns = <50>; 64*4882a593Smuzhiyun cdns,tchsh-ns = <4>; 65*4882a593Smuzhiyun cdns,tslch-ns = <4>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68