1*4882a593Smuzhiyun* Cadence NAND controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : "cdns,hp-nfc" 5*4882a593Smuzhiyun - reg : Contains two entries, each of which is a tuple consisting of a 6*4882a593Smuzhiyun physical address and length. The first entry is the address and 7*4882a593Smuzhiyun length of the controller register set. The second entry is the 8*4882a593Smuzhiyun address and length of the Slave DMA data port. 9*4882a593Smuzhiyun - reg-names: should contain "reg" and "sdma" 10*4882a593Smuzhiyun - #address-cells: should be 1. The cell encodes the chip select connection. 11*4882a593Smuzhiyun - #size-cells : should be 0. 12*4882a593Smuzhiyun - interrupts : The interrupt number. 13*4882a593Smuzhiyun - clocks: phandle of the controller core clock (nf_clk). 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun - dmas: shall reference DMA channel associated to the NAND controller 17*4882a593Smuzhiyun - cdns,board-delay-ps : Estimated Board delay. The value includes the total 18*4882a593Smuzhiyun round trip delay for the signals and is used for deciding on values 19*4882a593Smuzhiyun associated with data read capture. The example formula for SDR mode is 20*4882a593Smuzhiyun the following: 21*4882a593Smuzhiyun board delay = RE#PAD delay + PCB trace to device + PCB trace from device 22*4882a593Smuzhiyun + DQ PAD delay 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunChild nodes represent the available NAND chips. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunRequired properties of NAND chips: 27*4882a593Smuzhiyun - reg: shall contain the native Chip Select ids from 0 to max supported by 28*4882a593Smuzhiyun the cadence nand flash controller 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunSee Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on 31*4882a593Smuzhiyungeneric bindings. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunnand_controller: nand-controller@60000000 { 36*4882a593Smuzhiyun compatible = "cdns,hp-nfc"; 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <0>; 39*4882a593Smuzhiyun reg = <0x60000000 0x10000>, <0x80000000 0x10000>; 40*4882a593Smuzhiyun reg-names = "reg", "sdma"; 41*4882a593Smuzhiyun clocks = <&nf_clk>; 42*4882a593Smuzhiyun cdns,board-delay-ps = <4830>; 43*4882a593Smuzhiyun interrupts = <2 0>; 44*4882a593Smuzhiyun nand@0 { 45*4882a593Smuzhiyun reg = <0>; 46*4882a593Smuzhiyun label = "nand-1"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun nand@1 { 49*4882a593Smuzhiyun reg = <1>; 50*4882a593Smuzhiyun label = "nand-2"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun}; 54