1*4882a593SmuzhiyunAmlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis file documents the properties in addition to those available in 4*4882a593Smuzhiyunthe MTD NAND bindings. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : contains one of: 8*4882a593Smuzhiyun - "amlogic,meson-gxl-nfc" 9*4882a593Smuzhiyun - "amlogic,meson-axg-nfc" 10*4882a593Smuzhiyun- clocks : 11*4882a593Smuzhiyun A list of phandle + clock-specifier pairs for the clocks listed 12*4882a593Smuzhiyun in clock-names. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- clock-names: Should contain the following: 15*4882a593Smuzhiyun "core" - NFC module gate clock 16*4882a593Smuzhiyun "device" - device clock from eMMC sub clock controller 17*4882a593Smuzhiyun "rx" - rx clock phase 18*4882a593Smuzhiyun "tx" - tx clock phase 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC 21*4882a593Smuzhiyun controller port C 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional children nodes: 24*4882a593SmuzhiyunChildren nodes represent the available nand chips. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunOther properties: 27*4882a593Smuzhiyunsee Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample demonstrate on AXG SoC: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun sd_emmc_c_clkc: mmc@7000 { 32*4882a593Smuzhiyun compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; 33*4882a593Smuzhiyun reg = <0x0 0x7000 0x0 0x800>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun nand-controller@7800 { 37*4882a593Smuzhiyun compatible = "amlogic,meson-axg-nfc"; 38*4882a593Smuzhiyun reg = <0x0 0x7800 0x0 0x100>; 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun clocks = <&clkc CLKID_SD_EMMC_C>, 44*4882a593Smuzhiyun <&sd_emmc_c_clkc CLKID_MMC_DIV>, 45*4882a593Smuzhiyun <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, 46*4882a593Smuzhiyun <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; 47*4882a593Smuzhiyun clock-names = "core", "device", "rx", "tx"; 48*4882a593Smuzhiyun amlogic,mmc-syscon = <&sd_emmc_c_clkc>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun pinctrl-names = "default"; 51*4882a593Smuzhiyun pinctrl-0 = <&nand_pins>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun nand@0 { 54*4882a593Smuzhiyun reg = <0>; 55*4882a593Smuzhiyun #address-cells = <1>; 56*4882a593Smuzhiyun #size-cells = <1>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun nand-on-flash-bbt; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61