1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Synopsys Designware Mobile Storage Host Controller Common Properties 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunallOf: 10*4882a593Smuzhiyun - $ref: "mmc-controller.yaml#" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunmaintainers: 13*4882a593Smuzhiyun - Ulf Hansson <ulf.hansson@linaro.org> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun# Everything else is described in the common file 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun resets: 18*4882a593Smuzhiyun maxItems: 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reset-names: 21*4882a593Smuzhiyun const: reset 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clock-frequency: 24*4882a593Smuzhiyun description: 25*4882a593Smuzhiyun Should be the frequency (in Hz) of the ciu clock. If this 26*4882a593Smuzhiyun is specified and the ciu clock is specified then we'll try to set the ciu 27*4882a593Smuzhiyun clock to this at probe time. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun fifo-depth: 30*4882a593Smuzhiyun description: 31*4882a593Smuzhiyun The maximum size of the tx/rx fifo's. If this property is not 32*4882a593Smuzhiyun specified, the default value of the fifo size is determined from the 33*4882a593Smuzhiyun controller registers. 34*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun card-detect-delay: 37*4882a593Smuzhiyun description: 38*4882a593Smuzhiyun Delay in milli-seconds before detecting card after card 39*4882a593Smuzhiyun insert event. The default value is 0. 40*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 41*4882a593Smuzhiyun default: 0 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun data-addr: 44*4882a593Smuzhiyun description: 45*4882a593Smuzhiyun Override fifo address with value provided by DT. The default FIFO reg 46*4882a593Smuzhiyun offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) 47*4882a593Smuzhiyun by driver. If the controller does not follow this rule, please use 48*4882a593Smuzhiyun this property to set fifo address in device tree. 49*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun fifo-watermark-aligned: 52*4882a593Smuzhiyun description: 53*4882a593Smuzhiyun Data done irq is expected if data length is less than 54*4882a593Smuzhiyun watermark in PIO mode. But fifo watermark is requested to be aligned 55*4882a593Smuzhiyun with data length in some SoC so that TX/RX irq can be generated with 56*4882a593Smuzhiyun data done irq. Add this watermark quirk to mark this requirement and 57*4882a593Smuzhiyun force fifo watermark setting accordingly. 58*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/flag 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun dmas: 61*4882a593Smuzhiyun maxItems: 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun dma-names: 64*4882a593Smuzhiyun const: rx-tx 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunadditionalProperties: true 67