1*4882a593SmuzhiyunMOXA ART MMC Host Controller Interface 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun Inherits from mmc binding[1]. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun [1] Documentation/devicetree/bindings/mmc/mmc.txt 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible : Must be "moxa,moxart-mmc" or "faraday,ftsdc010" 10*4882a593Smuzhiyun- reg : Should contain registers location and length 11*4882a593Smuzhiyun- interrupts : Should contain the interrupt number 12*4882a593Smuzhiyun- clocks : Should contain phandle for the clock feeding the MMC controller 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunOptional properties: 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- dmas : Should contain two DMA channels, line request number must be 5 for 17*4882a593Smuzhiyun both channels 18*4882a593Smuzhiyun- dma-names : Must be "tx", "rx" 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun mmc: mmc@98e00000 { 23*4882a593Smuzhiyun compatible = "moxa,moxart-mmc"; 24*4882a593Smuzhiyun reg = <0x98e00000 0x5C>; 25*4882a593Smuzhiyun interrupts = <5 0>; 26*4882a593Smuzhiyun clocks = <&clk_apb>; 27*4882a593Smuzhiyun dmas = <&dma 5>, 28*4882a593Smuzhiyun <&dma 5>; 29*4882a593Smuzhiyun dma-names = "tx", "rx"; 30*4882a593Smuzhiyun }; 31