1*4882a593Smuzhiyun* ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe ARM PrimeCell MMCI PL180 and PL181 provides an interface for 4*4882a593Smuzhiyunreading and writing to MultiMedia and SD cards alike. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThis file documents differences between the core properties described 7*4882a593Smuzhiyunby mmc.txt and the properties used by the mmci driver. Using "st" as 8*4882a593Smuzhiyunthe prefix for a property, indicates support by the ST Micro variant. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible : contains "arm,pl18x", "arm,primecell". 12*4882a593Smuzhiyun- vmmc-supply : phandle to the regulator device tree node, mentioned 13*4882a593Smuzhiyun as the VCC/VDD supply in the eMMC/SD specs. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides 17*4882a593Smuzhiyun the ID provided by the HW 18*4882a593Smuzhiyun- resets : phandle to internal reset line. 19*4882a593Smuzhiyun Should be defined for sdmmc variant. 20*4882a593Smuzhiyun- vqmmc-supply : phandle to the regulator device tree node, mentioned 21*4882a593Smuzhiyun as the VCCQ/VDD_IO supply in the eMMC/SD specs. 22*4882a593Smuzhiyunspecific for ux500 variant: 23*4882a593Smuzhiyun- st,sig-dir-dat0 : bus signal direction pin used for DAT[0]. 24*4882a593Smuzhiyun- st,sig-dir-dat2 : bus signal direction pin used for DAT[2]. 25*4882a593Smuzhiyun- st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1]. 26*4882a593Smuzhiyun- st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7]. 27*4882a593Smuzhiyun- st,sig-dir-cmd : cmd signal direction pin used for CMD. 28*4882a593Smuzhiyun- st,sig-pin-fbclk : feedback clock signal pin used. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunspecific for sdmmc variant: 31*4882a593Smuzhiyun- reg : a second base register may be defined if a delay 32*4882a593Smuzhiyun block is present and used for tuning. 33*4882a593Smuzhiyun- st,sig-dir : signal direction polarity used for cmd, dat0 dat123. 34*4882a593Smuzhiyun- st,neg-edge : data & command phase relation, generated on 35*4882a593Smuzhiyun sd clock falling edge. 36*4882a593Smuzhiyun- st,use-ckin : use ckin pin from an external driver to sample 37*4882a593Smuzhiyun the receive data (example: with voltage 38*4882a593Smuzhiyun switch transceiver). 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunDeprecated properties: 41*4882a593Smuzhiyun- mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable. 42*4882a593Smuzhiyun- mmc-cap-sd-highspeed : indicates whether SD is high speed capable. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunExample: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunsdi0_per1@80126000 { 47*4882a593Smuzhiyun compatible = "arm,pl18x", "arm,primecell"; 48*4882a593Smuzhiyun reg = <0x80126000 0x1000>; 49*4882a593Smuzhiyun interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ 52*4882a593Smuzhiyun <&dma 29 0 0x0>; /* Logical - MemToDev */ 53*4882a593Smuzhiyun dma-names = "rx", "tx"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; 56*4882a593Smuzhiyun clock-names = "sdi", "apb_pclk"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun max-frequency = <100000000>; 59*4882a593Smuzhiyun bus-width = <4>; 60*4882a593Smuzhiyun cap-sd-highspeed; 61*4882a593Smuzhiyun cap-mmc-highspeed; 62*4882a593Smuzhiyun cd-gpios = <&gpio2 31 0x4>; // 95 63*4882a593Smuzhiyun st,sig-dir-dat0; 64*4882a593Smuzhiyun st,sig-dir-dat2; 65*4882a593Smuzhiyun st,sig-dir-cmd; 66*4882a593Smuzhiyun st,sig-pin-fbclk; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun vmmc-supply = <&ab8500_ldo_aux3_reg>; 69*4882a593Smuzhiyun vqmmc-supply = <&vmmci>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 72*4882a593Smuzhiyun pinctrl-0 = <&sdi0_default_mode>; 73*4882a593Smuzhiyun pinctrl-1 = <&sdi0_sleep_mode>; 74*4882a593Smuzhiyun}; 75