1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Microchip Sparx5 Mobile Storage Host Controller Binding 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunallOf: 10*4882a593Smuzhiyun - $ref: "mmc-controller.yaml" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunmaintainers: 13*4882a593Smuzhiyun - Lars Povlsen <lars.povlsen@microchip.com> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun# Everything else is described in the common file 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: microchip,dw-sparx5-sdhci 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun interrupts: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun description: 29*4882a593Smuzhiyun Handle to "core" clock for the sdhci controller. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clock-names: 32*4882a593Smuzhiyun items: 33*4882a593Smuzhiyun - const: core 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun microchip,clock-delay: 36*4882a593Smuzhiyun description: Delay clock to card to meet setup time requirements. 37*4882a593Smuzhiyun Each step increase by 1.25ns. 38*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 39*4882a593Smuzhiyun minimum: 1 40*4882a593Smuzhiyun maximum: 15 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunrequired: 43*4882a593Smuzhiyun - compatible 44*4882a593Smuzhiyun - reg 45*4882a593Smuzhiyun - interrupts 46*4882a593Smuzhiyun - clocks 47*4882a593Smuzhiyun - clock-names 48*4882a593Smuzhiyun 49*4882a593SmuzhiyununevaluatedProperties: false 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunexamples: 52*4882a593Smuzhiyun - | 53*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 54*4882a593Smuzhiyun #include <dt-bindings/clock/microchip,sparx5.h> 55*4882a593Smuzhiyun sdhci0: mmc@600800000 { 56*4882a593Smuzhiyun compatible = "microchip,dw-sparx5-sdhci"; 57*4882a593Smuzhiyun reg = <0x00800000 0x1000>; 58*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins>; 59*4882a593Smuzhiyun pinctrl-names = "default"; 60*4882a593Smuzhiyun clocks = <&clks CLK_ID_AUX1>; 61*4882a593Smuzhiyun clock-names = "core"; 62*4882a593Smuzhiyun assigned-clocks = <&clks CLK_ID_AUX1>; 63*4882a593Smuzhiyun assigned-clock-rates = <800000000>; 64*4882a593Smuzhiyun interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 65*4882a593Smuzhiyun bus-width = <8>; 66*4882a593Smuzhiyun microchip,clock-delay = <10>; 67*4882a593Smuzhiyun }; 68