1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Amlogic Meson SDHC controller Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunallOf: 10*4882a593Smuzhiyun - $ref: "mmc-controller.yaml" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunmaintainers: 13*4882a593Smuzhiyun - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyundescription: | 16*4882a593Smuzhiyun The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC 17*4882a593Smuzhiyun card interface with 1/4/8-bit bus width. 18*4882a593Smuzhiyun It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock). 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun items: 23*4882a593Smuzhiyun - enum: 24*4882a593Smuzhiyun - amlogic,meson8-sdhc 25*4882a593Smuzhiyun - amlogic,meson8b-sdhc 26*4882a593Smuzhiyun - amlogic,meson8m2-sdhc 27*4882a593Smuzhiyun - const: amlogic,meson-mx-sdhc 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun reg: 30*4882a593Smuzhiyun minItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun interrupts: 33*4882a593Smuzhiyun minItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clocks: 36*4882a593Smuzhiyun minItems: 5 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clock-names: 39*4882a593Smuzhiyun items: 40*4882a593Smuzhiyun - const: clkin0 41*4882a593Smuzhiyun - const: clkin1 42*4882a593Smuzhiyun - const: clkin2 43*4882a593Smuzhiyun - const: clkin3 44*4882a593Smuzhiyun - const: pclk 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunrequired: 47*4882a593Smuzhiyun - compatible 48*4882a593Smuzhiyun - reg 49*4882a593Smuzhiyun - interrupts 50*4882a593Smuzhiyun - clocks 51*4882a593Smuzhiyun - clock-names 52*4882a593Smuzhiyun 53*4882a593SmuzhiyununevaluatedProperties: false 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunexamples: 56*4882a593Smuzhiyun - | 57*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 58*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun sdhc: mmc@8e00 { 61*4882a593Smuzhiyun compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; 62*4882a593Smuzhiyun reg = <0x8e00 0x42>; 63*4882a593Smuzhiyun interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; 64*4882a593Smuzhiyun clocks = <&xtal>, 65*4882a593Smuzhiyun <&fclk_div4>, 66*4882a593Smuzhiyun <&fclk_div3>, 67*4882a593Smuzhiyun <&fclk_div5>, 68*4882a593Smuzhiyun <&sdhc_pclk>; 69*4882a593Smuzhiyun clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; 70*4882a593Smuzhiyun }; 71