1*4882a593SmuzhiyunAmlogic SD / eMMC controller for S905/GXBB family SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe MMC 5.1 compliant host controller on Amlogic provides the 4*4882a593Smuzhiyuninterface for SD, eMMC and SDIO devices. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThis file documents the properties in addition to those available in 7*4882a593Smuzhiyunthe MMC core bindings, documented by mmc.txt. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible : contains one of: 11*4882a593Smuzhiyun - "amlogic,meson-gx-mmc" 12*4882a593Smuzhiyun - "amlogic,meson-gxbb-mmc" 13*4882a593Smuzhiyun - "amlogic,meson-gxl-mmc" 14*4882a593Smuzhiyun - "amlogic,meson-gxm-mmc" 15*4882a593Smuzhiyun - "amlogic,meson-axg-mmc" 16*4882a593Smuzhiyun- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. 17*4882a593Smuzhiyun- clock-names: Should contain the following: 18*4882a593Smuzhiyun "core" - Main peripheral bus clock 19*4882a593Smuzhiyun "clkin0" - Parent clock of internal mux 20*4882a593Smuzhiyun "clkin1" - Other parent clock of internal mux 21*4882a593Smuzhiyun The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the 22*4882a593Smuzhiyun clock rate requested by the MMC core. 23*4882a593Smuzhiyun- resets : phandle of the internal reset line 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunOptional properties: 26*4882a593Smuzhiyun- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the 27*4882a593Smuzhiyun DRAM memory, like on the G12A dedicated SDIO controller. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun sd_emmc_a: mmc@70000 { 32*4882a593Smuzhiyun compatible = "amlogic,meson-gxbb-mmc"; 33*4882a593Smuzhiyun reg = <0x0 0x70000 0x0 0x2000>; 34*4882a593Smuzhiyun interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 35*4882a593Smuzhiyun clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; 36*4882a593Smuzhiyun clock-names = "core", "clkin0", "clkin1"; 37*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins>; 38*4882a593Smuzhiyun resets = <&reset RESET_SD_EMMC_A>; 39*4882a593Smuzhiyun }; 40