1*4882a593Smuzhiyun* QEMU PVPANIC MMIO Configuration bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunQEMU's emulation / virtualization targets provide the following PVPANIC 4*4882a593SmuzhiyunMMIO Configuration interface on the "virt" machine. 5*4882a593Smuzhiyuntype: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- a read-write, 16-bit wide data register. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunQEMU exposes the data register to guests as memory mapped registers. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- compatible: "qemu,pvpanic-mmio". 14*4882a593Smuzhiyun- reg: the MMIO region used by the device. 15*4882a593Smuzhiyun * Bytes 0x0 Write panic event to the reg when guest OS panics. 16*4882a593Smuzhiyun * Bytes 0x1 Reserved. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/ { 21*4882a593Smuzhiyun #size-cells = <0x2>; 22*4882a593Smuzhiyun #address-cells = <0x2>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun pvpanic-mmio@9060000 { 25*4882a593Smuzhiyun compatible = "qemu,pvpanic-mmio"; 26*4882a593Smuzhiyun reg = <0x0 0x9060000 0x0 0x2>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30