1*4882a593Smuzhiyun* Atmel SSC driver. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" 5*4882a593Smuzhiyun - atmel,at91rm9200-ssc: support pdc transfer 6*4882a593Smuzhiyun - atmel,at91sam9g45-ssc: support dma transfer 7*4882a593Smuzhiyun- reg: Should contain SSC registers location and length 8*4882a593Smuzhiyun- interrupts: Should contain SSC interrupt 9*4882a593Smuzhiyun- clock-names: tuple listing input clock names. 10*4882a593Smuzhiyun Required elements: "pclk" 11*4882a593Smuzhiyun- clocks: phandles to input clocks. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties for devices compatible with "atmel,at91sam9g45-ssc": 15*4882a593Smuzhiyun- dmas: DMA specifier, consisting of a phandle to DMA controller node, 16*4882a593Smuzhiyun the memory interface and SSC DMA channel ID (for tx and rx). 17*4882a593Smuzhiyun See Documentation/devicetree/bindings/dma/atmel-dma.txt for details. 18*4882a593Smuzhiyun- dma-names: Must be "tx", "rx". 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun - atmel,clk-from-rk-pin: bool property. 22*4882a593Smuzhiyun - When SSC works in slave mode, according to the hardware design, the 23*4882a593Smuzhiyun clock can get from TK pin, and also can get from RK pin. So, add 24*4882a593Smuzhiyun this parameter to choose where the clock from. 25*4882a593Smuzhiyun - By default the clock is from TK pin, if the clock from RK pin, this 26*4882a593Smuzhiyun property is needed. 27*4882a593Smuzhiyun - #sound-dai-cells: Should contain <0>. 28*4882a593Smuzhiyun - This property makes the SSC into an automatically registered DAI. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExamples: 31*4882a593Smuzhiyun- PDC transfer: 32*4882a593Smuzhiyunssc0: ssc@fffbc000 { 33*4882a593Smuzhiyun compatible = "atmel,at91rm9200-ssc"; 34*4882a593Smuzhiyun reg = <0xfffbc000 0x4000>; 35*4882a593Smuzhiyun interrupts = <14 4 5>; 36*4882a593Smuzhiyun clocks = <&ssc0_clk>; 37*4882a593Smuzhiyun clock-names = "pclk"; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun- DMA transfer: 41*4882a593Smuzhiyunssc0: ssc@f0010000 { 42*4882a593Smuzhiyun compatible = "atmel,at91sam9g45-ssc"; 43*4882a593Smuzhiyun reg = <0xf0010000 0x4000>; 44*4882a593Smuzhiyun interrupts = <28 4 5>; 45*4882a593Smuzhiyun dmas = <&dma0 1 13>, 46*4882a593Smuzhiyun <&dma0 1 14>; 47*4882a593Smuzhiyun dma-names = "tx", "rx"; 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 50*4882a593Smuzhiyun}; 51