1*4882a593SmuzhiyunLantiq XWAY SoC FPI BUS binding 2*4882a593Smuzhiyun============================ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun------------------------------------------------------------------------------- 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : Should be one of 8*4882a593Smuzhiyun "lantiq,xrx200-fpi" 9*4882a593Smuzhiyun- reg : The address and length of the XBAR 10*4882a593Smuzhiyun configuration register. 11*4882a593Smuzhiyun Address and length of the FPI bus itself. 12*4882a593Smuzhiyun- lantiq,rcu : A phandle to the RCU syscon 13*4882a593Smuzhiyun- lantiq,offset-endianness : Offset of the endianness configuration 14*4882a593Smuzhiyun register 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun------------------------------------------------------------------------------- 17*4882a593SmuzhiyunExample for the FPI on the xrx200 SoCs: 18*4882a593Smuzhiyun fpi@10000000 { 19*4882a593Smuzhiyun compatible = "lantiq,xrx200-fpi"; 20*4882a593Smuzhiyun ranges = <0x0 0x10000000 0xf000000>; 21*4882a593Smuzhiyun reg = <0x1f400000 0x1000>, 22*4882a593Smuzhiyun <0x10000000 0xf000000>; 23*4882a593Smuzhiyun lantiq,rcu = <&rcu0>; 24*4882a593Smuzhiyun lantiq,offset-endianness = <0x4c>; 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <1>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun gptu@e100a00 { 29*4882a593Smuzhiyun ...... 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32