1*4882a593SmuzhiyunImagination University Program MIPSfpga 2*4882a593Smuzhiyun======================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunUnder the Imagination University Program, a microAptiv UP core has been 5*4882a593Smuzhiyunreleased for academic usage. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunAs we are dealing with a MIPS core instantiated on an FPGA, specifications 8*4882a593Smuzhiyunare fluid and can be varied in RTL. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThis binding document is provided as baseline guidance for the example 11*4882a593Smuzhiyunproject provided by IMG. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunThe example project runs on the Nexys4DDR board by Digilent powered by 14*4882a593Smuzhiyunthe ARTIX-7 FPGA by Xilinx. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRelevant details about the example project and the Nexys4DDR board: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- microAptiv UP core m14Kc 19*4882a593Smuzhiyun- 50MHz clock speed 20*4882a593Smuzhiyun- 128Mbyte DDR RAM at 0x0000_0000 21*4882a593Smuzhiyun- 8Kbyte RAM at 0x1000_0000 22*4882a593Smuzhiyun- axi_intc at 0x1020_0000 23*4882a593Smuzhiyun- axi_uart16550 at 0x1040_0000 24*4882a593Smuzhiyun- axi_gpio at 0x1060_0000 25*4882a593Smuzhiyun- axi_i2c at 0x10A0_0000 26*4882a593Smuzhiyun- custom_gpio at 0x10C0_0000 27*4882a593Smuzhiyun- axi_ethernetlite at 0x10E0_0000 28*4882a593Smuzhiyun- 8Kbyte BootRAM at 0x1FC0_0000 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunRequired properties: 31*4882a593Smuzhiyun-------------------- 32*4882a593Smuzhiyun - compatible: Must include "digilent,nexys4ddr","img,xilfpga". 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunCPU nodes: 35*4882a593Smuzhiyun---------- 36*4882a593SmuzhiyunA "cpus" node is required. Required properties: 37*4882a593Smuzhiyun - #address-cells: Must be 1. 38*4882a593Smuzhiyun - #size-cells: Must be 0. 39*4882a593SmuzhiyunA CPU sub-node is also required for at least CPU 0. Required properties: 40*4882a593Smuzhiyun - device_type: Must be "cpu". 41*4882a593Smuzhiyun - compatible: Must be "mips,m14Kc". 42*4882a593Smuzhiyun - reg: Must be <0>. 43*4882a593Smuzhiyun - clocks: phandle to ext clock for fixed-clock received by MIPS core. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunExample: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun compatible = "img,xilfpga","digilent,nexys4ddr"; 48*4882a593Smuzhiyun cpus { 49*4882a593Smuzhiyun #address-cells = <1>; 50*4882a593Smuzhiyun #size-cells = <0>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun cpu0: cpu@0 { 53*4882a593Smuzhiyun device_type = "cpu"; 54*4882a593Smuzhiyun compatible = "mips,m14Kc"; 55*4882a593Smuzhiyun reg = <0>; 56*4882a593Smuzhiyun clocks = <&ext>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ext: ext { 61*4882a593Smuzhiyun compatible = "fixed-clock"; 62*4882a593Smuzhiyun #clock-cells = <0>; 63*4882a593Smuzhiyun clock-frequency = <50000000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunBoot protocol: 67*4882a593Smuzhiyun-------------- 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunThe BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. 70*4882a593SmuzhiyunThis is for easy reprogrammibility via JTAG. 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunThe BootRAM initializes the cache and the axi_uart peripheral. 73*4882a593Smuzhiyun 74*4882a593SmuzhiyunDDR initialization is already handled by a HW IP block. 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunWhen the example project bitstream is loaded, the cpu_reset button 77*4882a593Smuzhiyunneeds to be pressed. 78*4882a593Smuzhiyun 79*4882a593SmuzhiyunThe bootram initializes the cache and axi_uart. 80*4882a593SmuzhiyunThen outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board. 81*4882a593Smuzhiyun 82*4882a593SmuzhiyunAt this point, the board is ready to load the Linux kernel 83*4882a593Smuzhiyunvmlinux file via JTAG. 84