1*4882a593SmuzhiyunImagination Pistachio SoC 2*4882a593Smuzhiyun========================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun-------------------- 6*4882a593Smuzhiyun - compatible: Must include "img,pistachio". 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunCPU nodes: 9*4882a593Smuzhiyun---------- 10*4882a593SmuzhiyunA "cpus" node is required. Required properties: 11*4882a593Smuzhiyun - #address-cells: Must be 1. 12*4882a593Smuzhiyun - #size-cells: Must be 0. 13*4882a593SmuzhiyunA CPU sub-node is also required for at least CPU 0. Since the topology may 14*4882a593Smuzhiyunbe probed via CPS, it is not necessary to specify secondary CPUs. Required 15*4882a593Smuzhiyunpropertis: 16*4882a593Smuzhiyun - device_type: Must be "cpu". 17*4882a593Smuzhiyun - compatible: Must be "mti,interaptiv". 18*4882a593Smuzhiyun - reg: CPU number. 19*4882a593Smuzhiyun - clocks: Must include the CPU clock. See ../../clock/clock-bindings.txt for 20*4882a593Smuzhiyun details on clock bindings. 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun cpus { 23*4882a593Smuzhiyun #address-cells = <1>; 24*4882a593Smuzhiyun #size-cells = <0>; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun cpu0: cpu@0 { 27*4882a593Smuzhiyun device_type = "cpu"; 28*4882a593Smuzhiyun compatible = "mti,interaptiv"; 29*4882a593Smuzhiyun reg = <0>; 30*4882a593Smuzhiyun clocks = <&clk_core CLK_MIPS>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunBoot protocol: 36*4882a593Smuzhiyun-------------- 37*4882a593SmuzhiyunIn accordance with the MIPS UHI specification[1], the bootloader must pass the 38*4882a593Smuzhiyunfollowing arguments to the kernel: 39*4882a593Smuzhiyun - $a0: -2. 40*4882a593Smuzhiyun - $a1: KSEG0 address of the flattened device-tree blob. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun[1] http://prplfoundation.org/wiki/MIPS_documentation 43