1*4882a593Smuzhiyun* UCTL USB controller glue 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunProperties: 4*4882a593Smuzhiyun- compatible: "cavium,octeon-6335-uctl" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Compatibility with all cn6XXX SOCs. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- reg: The base address of the UCTL register bank. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- #address-cells: Must be <2>. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- #size-cells: Must be <2>. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- ranges: Empty to signify direct mapping of the children. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- refclk-frequency: A single cell containing the reference clock 17*4882a593Smuzhiyun frequency in Hz. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- refclk-type: A string describing the reference clock connection 20*4882a593Smuzhiyun either "crystal" or "external". 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun uctl@118006f000000 { 24*4882a593Smuzhiyun compatible = "cavium,octeon-6335-uctl"; 25*4882a593Smuzhiyun reg = <0x11800 0x6f000000 0x0 0x100>; 26*4882a593Smuzhiyun ranges; /* Direct mapping */ 27*4882a593Smuzhiyun #address-cells = <2>; 28*4882a593Smuzhiyun #size-cells = <2>; 29*4882a593Smuzhiyun /* 12MHz, 24MHz and 48MHz allowed */ 30*4882a593Smuzhiyun refclk-frequency = <24000000>; 31*4882a593Smuzhiyun /* Either "crystal" or "external" */ 32*4882a593Smuzhiyun refclk-type = "crystal"; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun ehci@16f0000000000 { 35*4882a593Smuzhiyun compatible = "cavium,octeon-6335-ehci","usb-ehci"; 36*4882a593Smuzhiyun reg = <0x16f00 0x00000000 0x0 0x100>; 37*4882a593Smuzhiyun interrupts = <0 56>; 38*4882a593Smuzhiyun big-endian-regs; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun ohci@16f0000000400 { 41*4882a593Smuzhiyun compatible = "cavium,octeon-6335-ohci","usb-ohci"; 42*4882a593Smuzhiyun reg = <0x16f00 0x00000400 0x0 0x100>; 43*4882a593Smuzhiyun interrupts = <0 56>; 44*4882a593Smuzhiyun big-endian-regs; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47