xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* UCTL SATA controller glue
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunUCTL is the bridge unit between the I/O interconnect (an internal bus)
4*4882a593Smuzhiyunand the SATA AHCI host controller (UAHC). It performs the following functions:
5*4882a593Smuzhiyun	- provides interfaces for the applications to access the UAHC AHCI
6*4882a593Smuzhiyun	  registers on the CN71XX I/O space.
7*4882a593Smuzhiyun	- provides a bridge for UAHC to fetch AHCI command table entries and data
8*4882a593Smuzhiyun	  buffers from Level 2 Cache.
9*4882a593Smuzhiyun	- posts interrupts to the CIU.
10*4882a593Smuzhiyun	- contains registers that:
11*4882a593Smuzhiyun		- control the behavior of the UAHC
12*4882a593Smuzhiyun		- control the clock/reset generation to UAHC
13*4882a593Smuzhiyun		- control endian swapping for all UAHC registers and DMA accesses
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunProperties:
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun- compatible: "cavium,octeon-7130-sata-uctl"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun  Compatibility with the cn7130 SOC.
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun- reg: The base address of the UCTL register bank.
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun- #address-cells, #size-cells, ranges and dma-ranges must be present and hold
24*4882a593Smuzhiyun	suitable values to map all child nodes.
25*4882a593Smuzhiyun
26*4882a593SmuzhiyunExample:
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	uctl@118006c000000 {
29*4882a593Smuzhiyun		compatible = "cavium,octeon-7130-sata-uctl";
30*4882a593Smuzhiyun		reg = <0x11800 0x6c000000 0x0 0x100>;
31*4882a593Smuzhiyun		ranges; /* Direct mapping */
32*4882a593Smuzhiyun		dma-ranges;
33*4882a593Smuzhiyun		#address-cells = <2>;
34*4882a593Smuzhiyun		#size-cells = <2>;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		sata: sata@16c0000000000 {
37*4882a593Smuzhiyun			compatible = "cavium,octeon-7130-ahci";
38*4882a593Smuzhiyun			reg = <0x16c00 0x00000000 0x0 0x200>;
39*4882a593Smuzhiyun			interrupt-parent = <&cibsata>;
40*4882a593Smuzhiyun			interrupts = <2 4>; /* Bit: 2, level */
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun	};
43