1*4882a593Smuzhiyun* DMA Engine. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Octeon DMA Engine transfers between the Boot Bus and main memory. 4*4882a593SmuzhiyunThe DMA Engine will be referred to by phandle by any device that is 5*4882a593Smuzhiyunconnected to it. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunProperties: 8*4882a593Smuzhiyun- compatible: "cavium,octeon-5750-bootbus-dma" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- reg: The base address of the DMA Engine's register bank. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- interrupts: A single interrupt specifier. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun dma0: dma-engine@1180000000100 { 18*4882a593Smuzhiyun compatible = "cavium,octeon-5750-bootbus-dma"; 19*4882a593Smuzhiyun reg = <0x11800 0x00000100 0x0 0x8>; 20*4882a593Smuzhiyun interrupts = <0 63>; 21*4882a593Smuzhiyun }; 22