1*4882a593Smuzhiyun* Cavium Interrupt Bus widget 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunProperties: 4*4882a593Smuzhiyun- compatible: "cavium,octeon-7130-cib" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Compatibility with cn70XX SoCs. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- interrupt-controller: This is an interrupt controller. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- reg: Two elements consisting of the addresses of the RAW and EN 11*4882a593Smuzhiyun registers of the CIB block 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- cavium,max-bits: The index (zero based) of the highest numbered bit 14*4882a593Smuzhiyun in the CIB block. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- interrupts: The CIU line to which the CIB block is connected. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- #interrupt-cells: Must be <2>. The first cell is the bit within the 19*4882a593Smuzhiyun CIB. The second cell specifies the triggering semantics of the 20*4882a593Smuzhiyun line. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun interrupt-controller@107000000e000 { 25*4882a593Smuzhiyun compatible = "cavium,octeon-7130-cib"; 26*4882a593Smuzhiyun reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */ 27*4882a593Smuzhiyun <0x10700 0x0000e100 0x0 0x8>; /* EN */ 28*4882a593Smuzhiyun cavium,max-bits = <23>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupt-controller; 31*4882a593Smuzhiyun interrupt-parent = <&ciu>; 32*4882a593Smuzhiyun interrupts = <1 24>; 33*4882a593Smuzhiyun /* Interrupts are specified by two parts: 34*4882a593Smuzhiyun * 1) Bit number in the CIB* registers 35*4882a593Smuzhiyun * 2) Triggering (1 - edge rising 36*4882a593Smuzhiyun * 2 - edge falling 37*4882a593Smuzhiyun * 4 - level active high 38*4882a593Smuzhiyun * 8 - level active low) 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #interrupt-cells = <2>; 41*4882a593Smuzhiyun }; 42