xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 Low-Power Timers bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyundescription: |
10*4882a593Smuzhiyun  The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
11*4882a593Smuzhiyun  functions
12*4882a593Smuzhiyun   - PWM output (with programmable prescaler, configurable polarity)
13*4882a593Smuzhiyun   - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14*4882a593Smuzhiyun   - Several counter modes:
15*4882a593Smuzhiyun     - quadrature encoder to detect angular position and direction of rotary
16*4882a593Smuzhiyun       elements, from IN1 and IN2 input signals.
17*4882a593Smuzhiyun     - simple counter from IN1 input signal.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyunmaintainers:
20*4882a593Smuzhiyun  - Fabrice Gasnier <fabrice.gasnier@st.com>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyunproperties:
23*4882a593Smuzhiyun  compatible:
24*4882a593Smuzhiyun    const: st,stm32-lptimer
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  reg:
27*4882a593Smuzhiyun    maxItems: 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  clocks:
30*4882a593Smuzhiyun    maxItems: 1
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  clock-names:
33*4882a593Smuzhiyun    items:
34*4882a593Smuzhiyun      - const: mux
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  interrupts:
37*4882a593Smuzhiyun    maxItems: 1
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  "#address-cells":
40*4882a593Smuzhiyun    const: 1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  "#size-cells":
43*4882a593Smuzhiyun    const: 0
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  wakeup-source: true
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun  pwm:
48*4882a593Smuzhiyun    type: object
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun    properties:
51*4882a593Smuzhiyun      compatible:
52*4882a593Smuzhiyun        const: st,stm32-pwm-lp
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun      "#pwm-cells":
55*4882a593Smuzhiyun        const: 3
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun    required:
58*4882a593Smuzhiyun      - "#pwm-cells"
59*4882a593Smuzhiyun      - compatible
60*4882a593Smuzhiyun
61*4882a593SmuzhiyunpatternProperties:
62*4882a593Smuzhiyun  "^trigger@[0-9]+$":
63*4882a593Smuzhiyun    type: object
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun    properties:
66*4882a593Smuzhiyun      compatible:
67*4882a593Smuzhiyun        const: st,stm32-lptimer-trigger
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun      reg:
70*4882a593Smuzhiyun        description: Identify trigger hardware block.
71*4882a593Smuzhiyun        items:
72*4882a593Smuzhiyun          minimum: 0
73*4882a593Smuzhiyun          maximum: 2
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun    required:
76*4882a593Smuzhiyun      - compatible
77*4882a593Smuzhiyun      - reg
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun  counter:
80*4882a593Smuzhiyun    type: object
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun    properties:
83*4882a593Smuzhiyun      compatible:
84*4882a593Smuzhiyun        const: st,stm32-lptimer-counter
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun    required:
87*4882a593Smuzhiyun      - compatible
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun  timer:
90*4882a593Smuzhiyun    type: object
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun    properties:
93*4882a593Smuzhiyun      compatible:
94*4882a593Smuzhiyun        const: st,stm32-lptimer-timer
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun    required:
97*4882a593Smuzhiyun      - compatible
98*4882a593Smuzhiyun
99*4882a593Smuzhiyunrequired:
100*4882a593Smuzhiyun  - "#address-cells"
101*4882a593Smuzhiyun  - "#size-cells"
102*4882a593Smuzhiyun  - compatible
103*4882a593Smuzhiyun  - reg
104*4882a593Smuzhiyun  - clocks
105*4882a593Smuzhiyun  - clock-names
106*4882a593Smuzhiyun
107*4882a593SmuzhiyunadditionalProperties: false
108*4882a593Smuzhiyun
109*4882a593Smuzhiyunexamples:
110*4882a593Smuzhiyun  - |
111*4882a593Smuzhiyun    #include <dt-bindings/clock/stm32mp1-clks.h>
112*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
113*4882a593Smuzhiyun    timer@40002400 {
114*4882a593Smuzhiyun      compatible = "st,stm32-lptimer";
115*4882a593Smuzhiyun      reg = <0x40002400 0x400>;
116*4882a593Smuzhiyun      clocks = <&timer_clk>;
117*4882a593Smuzhiyun      clock-names = "mux";
118*4882a593Smuzhiyun      interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
119*4882a593Smuzhiyun      #address-cells = <1>;
120*4882a593Smuzhiyun      #size-cells = <0>;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun      pwm {
123*4882a593Smuzhiyun        compatible = "st,stm32-pwm-lp";
124*4882a593Smuzhiyun        #pwm-cells = <3>;
125*4882a593Smuzhiyun      };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun      trigger@0 {
128*4882a593Smuzhiyun        compatible = "st,stm32-lptimer-trigger";
129*4882a593Smuzhiyun        reg = <0>;
130*4882a593Smuzhiyun      };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun      counter {
133*4882a593Smuzhiyun        compatible = "st,stm32-lptimer-counter";
134*4882a593Smuzhiyun      };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun      timer {
137*4882a593Smuzhiyun        compatible = "st,stm32-lptimer-timer";
138*4882a593Smuzhiyun      };
139*4882a593Smuzhiyun    };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun...
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