xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 Timers bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyundescription: |
10*4882a593Smuzhiyun  This hardware block provides 3 types of timer along with PWM functionality:
11*4882a593Smuzhiyun    - advanced-control timers consist of a 16-bit auto-reload counter driven
12*4882a593Smuzhiyun      by a programmable prescaler, break input feature, PWM outputs and
13*4882a593Smuzhiyun      complementary PWM outputs channels.
14*4882a593Smuzhiyun    - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15*4882a593Smuzhiyun      driven by a programmable prescaler and PWM outputs.
16*4882a593Smuzhiyun    - basic timers consist of a 16-bit auto-reload counter driven by a
17*4882a593Smuzhiyun      programmable prescaler.
18*4882a593Smuzhiyun
19*4882a593Smuzhiyunmaintainers:
20*4882a593Smuzhiyun  - Benjamin Gaignard <benjamin.gaignard@st.com>
21*4882a593Smuzhiyun  - Fabrice Gasnier <fabrice.gasnier@st.com>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyunproperties:
24*4882a593Smuzhiyun  compatible:
25*4882a593Smuzhiyun    const: st,stm32-timers
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  reg:
28*4882a593Smuzhiyun    maxItems: 1
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  clocks:
31*4882a593Smuzhiyun    maxItems: 1
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  clock-names:
34*4882a593Smuzhiyun    items:
35*4882a593Smuzhiyun      - const: int
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  reset:
38*4882a593Smuzhiyun    maxItems: 1
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  dmas:
41*4882a593Smuzhiyun    minItems: 1
42*4882a593Smuzhiyun    maxItems: 7
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  dma-names:
45*4882a593Smuzhiyun    items:
46*4882a593Smuzhiyun      enum: [ ch1, ch2, ch3, ch4, up, trig, com ]
47*4882a593Smuzhiyun    minItems: 1
48*4882a593Smuzhiyun    maxItems: 7
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  "#address-cells":
51*4882a593Smuzhiyun    const: 1
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  "#size-cells":
54*4882a593Smuzhiyun    const: 0
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  pwm:
57*4882a593Smuzhiyun    type: object
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun    properties:
60*4882a593Smuzhiyun      compatible:
61*4882a593Smuzhiyun        const: st,stm32-pwm
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun      "#pwm-cells":
64*4882a593Smuzhiyun        const: 3
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun      st,breakinput:
67*4882a593Smuzhiyun        description:
68*4882a593Smuzhiyun          One or two <index level filter> to describe break input
69*4882a593Smuzhiyun          configurations.
70*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/uint32-matrix
71*4882a593Smuzhiyun        items:
72*4882a593Smuzhiyun          items:
73*4882a593Smuzhiyun            - description: |
74*4882a593Smuzhiyun                "index" indicates on which break input (0 or 1) the
75*4882a593Smuzhiyun                configuration should be applied.
76*4882a593Smuzhiyun              enum: [0, 1]
77*4882a593Smuzhiyun            - description: |
78*4882a593Smuzhiyun                "level" gives the active level (0=low or 1=high) of the
79*4882a593Smuzhiyun                input signal for this configuration
80*4882a593Smuzhiyun              enum: [0, 1]
81*4882a593Smuzhiyun            - description: |
82*4882a593Smuzhiyun                "filter" gives the filtering value (up to 15) to be applied.
83*4882a593Smuzhiyun              maximum: 15
84*4882a593Smuzhiyun        minItems: 1
85*4882a593Smuzhiyun        maxItems: 2
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun    required:
88*4882a593Smuzhiyun      - "#pwm-cells"
89*4882a593Smuzhiyun      - compatible
90*4882a593Smuzhiyun
91*4882a593SmuzhiyunpatternProperties:
92*4882a593Smuzhiyun  "^timer@[0-9]+$":
93*4882a593Smuzhiyun    type: object
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun    properties:
96*4882a593Smuzhiyun      compatible:
97*4882a593Smuzhiyun        enum:
98*4882a593Smuzhiyun          - st,stm32-timer-trigger
99*4882a593Smuzhiyun          - st,stm32h7-timer-trigger
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun      reg:
102*4882a593Smuzhiyun        description: Identify trigger hardware block.
103*4882a593Smuzhiyun        items:
104*4882a593Smuzhiyun          minimum: 0
105*4882a593Smuzhiyun          maximum: 16
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun    required:
108*4882a593Smuzhiyun      - compatible
109*4882a593Smuzhiyun      - reg
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun  counter:
112*4882a593Smuzhiyun    type: object
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun    properties:
115*4882a593Smuzhiyun      compatible:
116*4882a593Smuzhiyun        const: st,stm32-timer-counter
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun    required:
119*4882a593Smuzhiyun      - compatible
120*4882a593Smuzhiyun
121*4882a593Smuzhiyunrequired:
122*4882a593Smuzhiyun  - "#address-cells"
123*4882a593Smuzhiyun  - "#size-cells"
124*4882a593Smuzhiyun  - compatible
125*4882a593Smuzhiyun  - reg
126*4882a593Smuzhiyun  - clocks
127*4882a593Smuzhiyun  - clock-names
128*4882a593Smuzhiyun
129*4882a593SmuzhiyunadditionalProperties: false
130*4882a593Smuzhiyun
131*4882a593Smuzhiyunexamples:
132*4882a593Smuzhiyun  - |
133*4882a593Smuzhiyun    #include <dt-bindings/clock/stm32mp1-clks.h>
134*4882a593Smuzhiyun    timers2: timers@40000000 {
135*4882a593Smuzhiyun      #address-cells = <1>;
136*4882a593Smuzhiyun      #size-cells = <0>;
137*4882a593Smuzhiyun      compatible = "st,stm32-timers";
138*4882a593Smuzhiyun      reg = <0x40000000 0x400>;
139*4882a593Smuzhiyun      clocks = <&rcc TIM2_K>;
140*4882a593Smuzhiyun      clock-names = "int";
141*4882a593Smuzhiyun      dmas = <&dmamux1 18 0x400 0x1>,
142*4882a593Smuzhiyun             <&dmamux1 19 0x400 0x1>,
143*4882a593Smuzhiyun             <&dmamux1 20 0x400 0x1>,
144*4882a593Smuzhiyun             <&dmamux1 21 0x400 0x1>,
145*4882a593Smuzhiyun             <&dmamux1 22 0x400 0x1>;
146*4882a593Smuzhiyun      dma-names = "ch1", "ch2", "ch3", "ch4", "up";
147*4882a593Smuzhiyun      pwm {
148*4882a593Smuzhiyun        compatible = "st,stm32-pwm";
149*4882a593Smuzhiyun        #pwm-cells = <3>;
150*4882a593Smuzhiyun        st,breakinput = <0 1 5>;
151*4882a593Smuzhiyun      };
152*4882a593Smuzhiyun      timer@0 {
153*4882a593Smuzhiyun        compatible = "st,stm32-timer-trigger";
154*4882a593Smuzhiyun        reg = <0>;
155*4882a593Smuzhiyun      };
156*4882a593Smuzhiyun      counter {
157*4882a593Smuzhiyun        compatible = "st,stm32-timer-counter";
158*4882a593Smuzhiyun      };
159*4882a593Smuzhiyun    };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun...
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