1*4882a593SmuzhiyunSamsung Exynos SoC Low Power Audio Subsystem (LPASS) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible : "samsung,exynos5433-lpass" 6*4882a593Smuzhiyun - reg : should contain the LPASS top SFR region location 7*4882a593Smuzhiyun and size 8*4882a593Smuzhiyun - clock-names : should contain following required clocks: "sfr0_ctrl" 9*4882a593Smuzhiyun - clocks : should contain clock specifiers of all clocks, which 10*4882a593Smuzhiyun input names have been specified in clock-names 11*4882a593Smuzhiyun property, in same order. 12*4882a593Smuzhiyun - #address-cells : should be 1 13*4882a593Smuzhiyun - #size-cells : should be 1 14*4882a593Smuzhiyun - ranges : must be present 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunEach IP block of the Low Power Audio Subsystem should be specified as 17*4882a593Smuzhiyunan optional sub-node. For "samsung,exynos5433-lpass" compatible this includes: 18*4882a593SmuzhiyunUART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunBindings of the sub-nodes are described in: 21*4882a593Smuzhiyun ../serial/samsung_uart.yaml 22*4882a593Smuzhiyun ../sound/samsung-i2s.txt 23*4882a593Smuzhiyun ../dma/arm-pl330.txt 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunaudio-subsystem { 29*4882a593Smuzhiyun compatible = "samsung,exynos5433-lpass"; 30*4882a593Smuzhiyun reg = <0x11400000 0x100>, <0x11500000 0x08>; 31*4882a593Smuzhiyun clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; 32*4882a593Smuzhiyun clock-names = "sfr0_ctrl"; 33*4882a593Smuzhiyun #address-cells = <1>; 34*4882a593Smuzhiyun #size-cells = <1>; 35*4882a593Smuzhiyun ranges; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun adma: adma@11420000 { 38*4882a593Smuzhiyun compatible = "arm,pl330", "arm,primecell"; 39*4882a593Smuzhiyun reg = <0x11420000 0x1000>; 40*4882a593Smuzhiyun interrupts = <0 73 0>; 41*4882a593Smuzhiyun clocks = <&cmu_aud CLK_ACLK_DMAC>; 42*4882a593Smuzhiyun clock-names = "apb_pclk"; 43*4882a593Smuzhiyun #dma-cells = <1>; 44*4882a593Smuzhiyun #dma-channels = <8>; 45*4882a593Smuzhiyun #dma-requests = <32>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun i2s0: i2s0@11440000 { 49*4882a593Smuzhiyun compatible = "samsung,exynos7-i2s"; 50*4882a593Smuzhiyun reg = <0x11440000 0x100>; 51*4882a593Smuzhiyun dmas = <&adma 0 &adma 2>; 52*4882a593Smuzhiyun dma-names = "tx", "rx"; 53*4882a593Smuzhiyun interrupts = <0 70 0>; 54*4882a593Smuzhiyun clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, 55*4882a593Smuzhiyun <&cmu_aud CLK_SCLK_AUD_I2S>, 56*4882a593Smuzhiyun <&cmu_aud CLK_SCLK_I2S_BCLK>; 57*4882a593Smuzhiyun clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun pinctrl-0 = <&i2s0_bus>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun serial_3: serial@11460000 { 63*4882a593Smuzhiyun compatible = "samsung,exynos5433-uart"; 64*4882a593Smuzhiyun reg = <0x11460000 0x100>; 65*4882a593Smuzhiyun interrupts = <0 67 0>; 66*4882a593Smuzhiyun clocks = <&cmu_aud CLK_PCLK_AUD_UART>, 67*4882a593Smuzhiyun <&cmu_aud CLK_SCLK_AUD_UART>; 68*4882a593Smuzhiyun clock-names = "uart", "clk_uart_baud0"; 69*4882a593Smuzhiyun pinctrl-names = "default"; 70*4882a593Smuzhiyun pinctrl-0 = <&uart_aud_bus>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73