1*4882a593Smuzhiyun Qualcomm SPMI PMICs multi-function device bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084 4*4882a593SmuzhiyunPMICs. These PMICs use a QPNP scheme through SPMI interface. 5*4882a593SmuzhiyunQPNP is effectively a partitioning scheme for dividing the SPMI extended 6*4882a593Smuzhiyunregister space up into logical pieces, and set of fixed register 7*4882a593Smuzhiyunlocations/definitions within these regions, with some of these regions 8*4882a593Smuzhiyunspecifically used for interrupt handling. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThe QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are 11*4882a593Smuzhiyuninterfaced to the chip via the SPMI (System Power Management Interface) bus. 12*4882a593SmuzhiyunSupport for multiple independent functions are implemented by splitting the 13*4882a593Smuzhiyun16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes 14*4882a593Smuzhiyuneach. A function can consume one or more of these fixed-size register regions. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties: 17*4882a593Smuzhiyun- compatible: Should contain one of: 18*4882a593Smuzhiyun "qcom,pm8941", 19*4882a593Smuzhiyun "qcom,pm8841", 20*4882a593Smuzhiyun "qcom,pma8084", 21*4882a593Smuzhiyun "qcom,pm8019", 22*4882a593Smuzhiyun "qcom,pm8226", 23*4882a593Smuzhiyun "qcom,pm8110", 24*4882a593Smuzhiyun "qcom,pma8084", 25*4882a593Smuzhiyun "qcom,pmi8962", 26*4882a593Smuzhiyun "qcom,pmd9635", 27*4882a593Smuzhiyun "qcom,pm8994", 28*4882a593Smuzhiyun "qcom,pmi8994", 29*4882a593Smuzhiyun "qcom,pm8916", 30*4882a593Smuzhiyun "qcom,pm8004", 31*4882a593Smuzhiyun "qcom,pm8909", 32*4882a593Smuzhiyun "qcom,pm8950", 33*4882a593Smuzhiyun "qcom,pmi8950", 34*4882a593Smuzhiyun "qcom,pm8998", 35*4882a593Smuzhiyun "qcom,pmi8998", 36*4882a593Smuzhiyun "qcom,pm8005", 37*4882a593Smuzhiyun or generalized "qcom,spmi-pmic". 38*4882a593Smuzhiyun- reg: Specifies the SPMI USID slave address for this device. 39*4882a593Smuzhiyun For more information see: 40*4882a593Smuzhiyun Documentation/devicetree/bindings/spmi/spmi.yaml 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunRequired properties for peripheral child nodes: 43*4882a593Smuzhiyun- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunOptional properties for peripheral child nodes: 46*4882a593Smuzhiyun- interrupts: Interrupts are specified as a 4-tuple. For more information 47*4882a593Smuzhiyun see: 48*4882a593Smuzhiyun Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt 49*4882a593Smuzhiyun- interrupt-names: Corresponding interrupt name to the interrupts property 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunEach child node of SPMI slave id represents a function of the PMIC. In the 52*4882a593Smuzhiyunexample below the rtc device node represents a peripheral of pm8941 53*4882a593SmuzhiyunSID = 0. The regulator device node represents a peripheral of pm8941 SID = 1. 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExample: 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun spmi { 58*4882a593Smuzhiyun compatible = "qcom,spmi-pmic-arb"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun pm8941@0 { 61*4882a593Smuzhiyun compatible = "qcom,pm8941", "qcom,spmi-pmic"; 62*4882a593Smuzhiyun reg = <0x0 SPMI_USID>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun rtc { 65*4882a593Smuzhiyun compatible = "qcom,rtc"; 66*4882a593Smuzhiyun interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; 67*4882a593Smuzhiyun interrupt-names = "alarm"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pm8941@1 { 72*4882a593Smuzhiyun compatible = "qcom,pm8941", "qcom,spmi-pmic"; 73*4882a593Smuzhiyun reg = <0x1 SPMI_USID>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun regulator { 76*4882a593Smuzhiyun compatible = "qcom,regulator"; 77*4882a593Smuzhiyun regulator-name = "8941_boost"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81