xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/max77620.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunMAX77620 Power management IC from Maxim Semiconductor.
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun-------------------
5*4882a593Smuzhiyun- compatible: Must be one of
6*4882a593Smuzhiyun		"maxim,max77620"
7*4882a593Smuzhiyun		"maxim,max20024"
8*4882a593Smuzhiyun		"maxim,max77663"
9*4882a593Smuzhiyun- reg: I2C device address.
10*4882a593Smuzhiyun
11*4882a593SmuzhiyunOptional properties:
12*4882a593Smuzhiyun-------------------
13*4882a593Smuzhiyun- interrupts:		The interrupt on the parent the controller is
14*4882a593Smuzhiyun			connected to.
15*4882a593Smuzhiyun- interrupt-controller: Marks the device node as an interrupt controller.
16*4882a593Smuzhiyun- #interrupt-cells:	is <2> and their usage is compliant to the 2 cells
17*4882a593Smuzhiyun			variant of <../interrupt-controller/interrupts.txt>
18*4882a593Smuzhiyun			IRQ numbers for different interrupt source of MAX77620
19*4882a593Smuzhiyun			are defined at dt-bindings/mfd/max77620.h.
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun- system-power-controller: Indicates that this PMIC is controlling the
22*4882a593Smuzhiyun			   system power, see [1] for more details.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/power/power-controller.txt
25*4882a593Smuzhiyun
26*4882a593SmuzhiyunOptional subnodes and their properties:
27*4882a593Smuzhiyun=======================================
28*4882a593Smuzhiyun
29*4882a593SmuzhiyunFlexible power sequence configurations:
30*4882a593Smuzhiyun--------------------------------------
31*4882a593SmuzhiyunThe Flexible Power Sequencer (FPS) allows each regulator to power up under
32*4882a593Smuzhiyunhardware or software control. Additionally, each regulator can power on
33*4882a593Smuzhiyunindependently or among a group of other regulators with an adjustable power-up
34*4882a593Smuzhiyunand power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
35*4882a593Smuzhiyunto be part of a sequence allowing external regulators to be sequenced along
36*4882a593Smuzhiyunwith internal regulators. 32KHz clock can be programmed to be part of a
37*4882a593Smuzhiyunsequence.
38*4882a593Smuzhiyun
39*4882a593SmuzhiyunThe flexible sequencing structure consists of two hardware enable inputs
40*4882a593Smuzhiyun(EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.
41*4882a593SmuzhiyunEach master sequencing timer is programmable through its configuration
42*4882a593Smuzhiyunregister to have a hardware enable source (EN1 or EN2) or a software enable
43*4882a593Smuzhiyunsource (SW). When enabled/disabled, the master sequencing timer generates
44*4882a593Smuzhiyuneight sequencing events on different time periods called slots. The time
45*4882a593Smuzhiyunperiod between each event is programmable within the configuration register.
46*4882a593SmuzhiyunEach regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
47*4882a593Smuzhiyunsequence slave register which allows its enable source to be specified as
48*4882a593Smuzhiyuna flexible power sequencer timer or a software bit. When a FPS source of
49*4882a593Smuzhiyunregulators, GPIOs and clocks specifies the enable source to be a flexible
50*4882a593Smuzhiyunpower sequencer, the power up and power down delays can be specified in
51*4882a593Smuzhiyunthe regulators, GPIOs and clocks flexible power sequencer configuration
52*4882a593Smuzhiyunregisters.
53*4882a593Smuzhiyun
54*4882a593SmuzhiyunWhen FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
55*4882a593Smuzhiyunclock are set into following state at the sequencing event that
56*4882a593Smuzhiyuncorresponds to its flexible sequencer configuration register.
57*4882a593Smuzhiyun	Sleep state: 			In this state, regulators, GPIOs
58*4882a593Smuzhiyun					and 32KHz clock get disabled at
59*4882a593Smuzhiyun					the sequencing event.
60*4882a593Smuzhiyun	Global Low Power Mode (GLPM):	In this state, regulators are set in
61*4882a593Smuzhiyun					low power mode at the sequencing event.
62*4882a593Smuzhiyun
63*4882a593SmuzhiyunThe configuration parameters of FPS is provided through sub-node "fps"
64*4882a593Smuzhiyunand their child for FPS specific. The child node name for FPS are "fps0",
65*4882a593Smuzhiyun"fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
66*4882a593Smuzhiyun
67*4882a593SmuzhiyunThe FPS configurations like FPS source, power up and power down slots for
68*4882a593Smuzhiyunregulators, GPIOs and 32kHz clocks are provided in their respective
69*4882a593Smuzhiyunconfiguration nodes which is explained in respective sub-system DT
70*4882a593Smuzhiyunbinding document.
71*4882a593Smuzhiyun
72*4882a593SmuzhiyunThere is need for different FPS configuration parameters based on system
73*4882a593Smuzhiyunstate like when system state changed from active to suspend or active to
74*4882a593Smuzhiyunpower off (shutdown).
75*4882a593Smuzhiyun
76*4882a593SmuzhiyunOptional properties:
77*4882a593Smuzhiyun-------------------
78*4882a593Smuzhiyun-maxim,fps-event-source:		u32, FPS event source like external
79*4882a593Smuzhiyun					hardware input to PMIC i.e. EN0, EN1 or
80*4882a593Smuzhiyun					software (SW).
81*4882a593Smuzhiyun					The macros are defined on
82*4882a593Smuzhiyun						dt-bindings/mfd/max77620.h
83*4882a593Smuzhiyun					for different control source.
84*4882a593Smuzhiyun					- MAX77620_FPS_EVENT_SRC_EN0
85*4882a593Smuzhiyun						for hardware input pin EN0.
86*4882a593Smuzhiyun					- MAX77620_FPS_EVENT_SRC_EN1
87*4882a593Smuzhiyun						for hardware input pin EN1.
88*4882a593Smuzhiyun					- MAX77620_FPS_EVENT_SRC_SW
89*4882a593Smuzhiyun						for software control.
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun-maxim,shutdown-fps-time-period-us:	u32, FPS time period in microseconds
92*4882a593Smuzhiyun					when system enters in to shutdown
93*4882a593Smuzhiyun					state.
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun-maxim,suspend-fps-time-period-us:	u32, FPS time period in microseconds
96*4882a593Smuzhiyun					when system enters in to suspend state.
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun-maxim,device-state-on-disabled-event:	u32, describe the PMIC state when FPS
99*4882a593Smuzhiyun					event cleared (set to LOW) whether it
100*4882a593Smuzhiyun					should go to sleep state or low-power
101*4882a593Smuzhiyun					state. Following are valid values:
102*4882a593Smuzhiyun					- MAX77620_FPS_INACTIVE_STATE_SLEEP
103*4882a593Smuzhiyun						to set the PMIC state to sleep.
104*4882a593Smuzhiyun					- MAX77620_FPS_INACTIVE_STATE_LOW_POWER
105*4882a593Smuzhiyun						to set the PMIC state to low
106*4882a593Smuzhiyun						power.
107*4882a593Smuzhiyun					Absence of this property or other value
108*4882a593Smuzhiyun					will not change device state when FPS
109*4882a593Smuzhiyun					event get cleared.
110*4882a593Smuzhiyun
111*4882a593SmuzhiyunHere supported time periods by device in microseconds are as follows:
112*4882a593SmuzhiyunMAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
113*4882a593SmuzhiyunMAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
114*4882a593SmuzhiyunMAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun-maxim,power-ok-control: configure map power ok bit
117*4882a593Smuzhiyun			1: Enables POK(Power OK) to control nRST_IO and GPIO1
118*4882a593Smuzhiyun			POK function.
119*4882a593Smuzhiyun			0: Disables POK control.
120*4882a593Smuzhiyun			if property missing, do not configure MPOK bit.
121*4882a593Smuzhiyun			If POK mapping is enabled for GPIO1/nRST_IO then,
122*4882a593Smuzhiyun			GPIO1/nRST_IO pins are HIGH only if all rails
123*4882a593Smuzhiyun			that have POK control enabled are HIGH.
124*4882a593Smuzhiyun			If any of the rails goes down(which are enabled for POK
125*4882a593Smuzhiyun			control) then, GPIO1/nRST_IO goes LOW.
126*4882a593Smuzhiyun			this property is valid for max20024 only.
127*4882a593Smuzhiyun
128*4882a593SmuzhiyunFor DT binding details of different sub modules like GPIO, pincontrol,
129*4882a593Smuzhiyunregulator, power, please refer respective device-tree binding document
130*4882a593Smuzhiyununder their respective sub-system directories.
131*4882a593Smuzhiyun
132*4882a593SmuzhiyunExample:
133*4882a593Smuzhiyun--------
134*4882a593Smuzhiyun#include <dt-bindings/mfd/max77620.h>
135*4882a593Smuzhiyun
136*4882a593Smuzhiyunmax77620@3c {
137*4882a593Smuzhiyun	compatible = "maxim,max77620";
138*4882a593Smuzhiyun	reg = <0x3c>;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun	interrupt-parent = <&intc>;
141*4882a593Smuzhiyun	interrupts = <0 86 IRQ_TYPE_NONE>;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	interrupt-controller;
144*4882a593Smuzhiyun	#interrupt-cells = <2>;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	fps {
147*4882a593Smuzhiyun		fps0 {
148*4882a593Smuzhiyun			maxim,shutdown-fps-time-period-us = <1280>;
149*4882a593Smuzhiyun			maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
150*4882a593Smuzhiyun		};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun		fps1 {
153*4882a593Smuzhiyun			maxim,shutdown-fps-time-period-us = <1280>;
154*4882a593Smuzhiyun			maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
155*4882a593Smuzhiyun		};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun		fps2 {
158*4882a593Smuzhiyun			maxim,shutdown-fps-time-period-us = <1280>;
159*4882a593Smuzhiyun			maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
160*4882a593Smuzhiyun		};
161*4882a593Smuzhiyun	};
162*4882a593Smuzhiyun};
163