1*4882a593Smuzhiyun* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties for USART: 4*4882a593Smuzhiyun- compatible: Should be one of the following: 5*4882a593Smuzhiyun - "atmel,at91rm9200-usart" 6*4882a593Smuzhiyun - "atmel,at91sam9260-usart" 7*4882a593Smuzhiyun - "microchip,sam9x60-usart" 8*4882a593Smuzhiyun - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" 9*4882a593Smuzhiyun - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" 10*4882a593Smuzhiyun - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" 11*4882a593Smuzhiyun- reg: Should contain registers location and length 12*4882a593Smuzhiyun- interrupts: Should contain interrupt 13*4882a593Smuzhiyun- clock-names: tuple listing input clock names. 14*4882a593Smuzhiyun Required elements: "usart" 15*4882a593Smuzhiyun- clocks: phandles to input clocks. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunRequired properties for USART in SPI mode: 18*4882a593Smuzhiyun- #size-cells : Must be <0> 19*4882a593Smuzhiyun- #address-cells : Must be <1> 20*4882a593Smuzhiyun- cs-gpios: chipselects (internal cs not supported) 21*4882a593Smuzhiyun- atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h) 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties in serial and SPI mode: 24*4882a593Smuzhiyun- dma bindings for dma transfer: 25*4882a593Smuzhiyun - dmas: DMA specifier, consisting of a phandle to DMA controller node, 26*4882a593Smuzhiyun memory peripheral interface and USART DMA channel ID, FIFO configuration. 27*4882a593Smuzhiyun The order of DMA channels is fixed. The first DMA channel must be TX 28*4882a593Smuzhiyun associated channel and the second one must be RX associated channel. 29*4882a593Smuzhiyun Refer to dma.txt and atmel-dma.txt for details. 30*4882a593Smuzhiyun - dma-names: "tx" for TX channel. 31*4882a593Smuzhiyun "rx" for RX channel. 32*4882a593Smuzhiyun The order of dma-names is also fixed. The first name must be "tx" 33*4882a593Smuzhiyun and the second one must be "rx" as in the examples below. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunOptional properties in serial mode: 36*4882a593Smuzhiyun- atmel,use-dma-rx: use of PDC or DMA for receiving data 37*4882a593Smuzhiyun- atmel,use-dma-tx: use of PDC or DMA for transmitting data 38*4882a593Smuzhiyun- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. 39*4882a593Smuzhiyun It will use specified PIO instead of the peripheral function pin for the USART feature. 40*4882a593Smuzhiyun If unsure, don't specify this property. 41*4882a593Smuzhiyun- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO 42*4882a593Smuzhiyun capable USARTs. 43*4882a593Smuzhiyun- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun<chip> compatible description: 46*4882a593Smuzhiyun- at91rm9200: legacy USART support 47*4882a593Smuzhiyun- at91sam9260: generic USART implementation for SAM9 SoCs 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunExample: 50*4882a593Smuzhiyun- use PDC: 51*4882a593Smuzhiyun usart0: serial@fff8c000 { 52*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 53*4882a593Smuzhiyun reg = <0xfff8c000 0x4000>; 54*4882a593Smuzhiyun interrupts = <7>; 55*4882a593Smuzhiyun clocks = <&usart0_clk>; 56*4882a593Smuzhiyun clock-names = "usart"; 57*4882a593Smuzhiyun atmel,use-dma-rx; 58*4882a593Smuzhiyun atmel,use-dma-tx; 59*4882a593Smuzhiyun rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; 60*4882a593Smuzhiyun cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; 61*4882a593Smuzhiyun dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; 62*4882a593Smuzhiyun dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; 63*4882a593Smuzhiyun dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; 64*4882a593Smuzhiyun rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun- use DMA: 68*4882a593Smuzhiyun usart0: serial@f001c000 { 69*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 70*4882a593Smuzhiyun reg = <0xf001c000 0x100>; 71*4882a593Smuzhiyun interrupts = <12 4 5>; 72*4882a593Smuzhiyun clocks = <&usart0_clk>; 73*4882a593Smuzhiyun clock-names = "usart"; 74*4882a593Smuzhiyun atmel,use-dma-rx; 75*4882a593Smuzhiyun atmel,use-dma-tx; 76*4882a593Smuzhiyun dmas = <&dma0 2 0x3>, 77*4882a593Smuzhiyun <&dma0 2 0x204>; 78*4882a593Smuzhiyun dma-names = "tx", "rx"; 79*4882a593Smuzhiyun atmel,fifo-size = <32>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun- SPI mode: 83*4882a593Smuzhiyun #include <dt-bindings/mfd/at91-usart.h> 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun spi0: spi@f001c000 { 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <0>; 88*4882a593Smuzhiyun compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; 89*4882a593Smuzhiyun atmel,usart-mode = <AT91_USART_MODE_SPI>; 90*4882a593Smuzhiyun reg = <0xf001c000 0x100>; 91*4882a593Smuzhiyun interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 92*4882a593Smuzhiyun clocks = <&usart0_clk>; 93*4882a593Smuzhiyun clock-names = "usart"; 94*4882a593Smuzhiyun dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, 95*4882a593Smuzhiyun <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; 96*4882a593Smuzhiyun dma-names = "tx", "rx"; 97*4882a593Smuzhiyun cs-gpios = <&pioB 3 0>; 98*4882a593Smuzhiyun }; 99