1*4882a593SmuzhiyunDevice-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: value should be one of the following: 5*4882a593Smuzhiyun "atmel,at91sam9n12-hlcdc" 6*4882a593Smuzhiyun "atmel,at91sam9x5-hlcdc" 7*4882a593Smuzhiyun "atmel,sama5d2-hlcdc" 8*4882a593Smuzhiyun "atmel,sama5d3-hlcdc" 9*4882a593Smuzhiyun "atmel,sama5d4-hlcdc" 10*4882a593Smuzhiyun "microchip,sam9x60-hlcdc" 11*4882a593Smuzhiyun - reg: base address and size of the HLCDC device registers. 12*4882a593Smuzhiyun - clock-names: the name of the 3 clocks requested by the HLCDC device. 13*4882a593Smuzhiyun Should contain "periph_clk", "sys_clk" and "slow_clk". 14*4882a593Smuzhiyun - clocks: should contain the 3 clocks requested by the HLCDC device. 15*4882a593Smuzhiyun - interrupts: should contain the description of the HLCDC interrupt line 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunThe HLCDC IP exposes two subdevices: 18*4882a593Smuzhiyun - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt 19*4882a593Smuzhiyun - a Display Controller: see ../display/atmel/hlcdc-dc.txt 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun hlcdc: hlcdc@f0030000 { 24*4882a593Smuzhiyun compatible = "atmel,sama5d3-hlcdc"; 25*4882a593Smuzhiyun reg = <0xf0030000 0x2000>; 26*4882a593Smuzhiyun clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; 27*4882a593Smuzhiyun clock-names = "periph_clk","sys_clk", "slow_clk"; 28*4882a593Smuzhiyun interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun hlcdc-display-controller { 31*4882a593Smuzhiyun compatible = "atmel,hlcdc-display-controller"; 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <0>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun port@0 { 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <0>; 40*4882a593Smuzhiyun reg = <0>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun hlcdc_panel_output: endpoint@0 { 43*4882a593Smuzhiyun reg = <0>; 44*4882a593Smuzhiyun remote-endpoint = <&panel_input>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun hlcdc_pwm: hlcdc-pwm { 50*4882a593Smuzhiyun compatible = "atmel,hlcdc-pwm"; 51*4882a593Smuzhiyun pinctrl-names = "default"; 52*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lcd_pwm>; 53*4882a593Smuzhiyun #pwm-cells = <3>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56