1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun# Copyright (c) 2020 MediaTek Inc.
3*4882a593Smuzhiyun%YAML 1.2
4*4882a593Smuzhiyun---
5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
7*4882a593Smuzhiyun
8*4882a593Smuzhiyuntitle: SMI (Smart Multimedia Interface) Local Arbiter
9*4882a593Smuzhiyun
10*4882a593Smuzhiyunmaintainers:
11*4882a593Smuzhiyun  - Yong Wu <yong.wu@mediatek.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    oneOf:
19*4882a593Smuzhiyun      - enum:
20*4882a593Smuzhiyun          - mediatek,mt2701-smi-larb
21*4882a593Smuzhiyun          - mediatek,mt2712-smi-larb
22*4882a593Smuzhiyun          - mediatek,mt6779-smi-larb
23*4882a593Smuzhiyun          - mediatek,mt8167-smi-larb
24*4882a593Smuzhiyun          - mediatek,mt8173-smi-larb
25*4882a593Smuzhiyun          - mediatek,mt8183-smi-larb
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun      - description: for mt7623
28*4882a593Smuzhiyun        items:
29*4882a593Smuzhiyun          - const: mediatek,mt7623-smi-larb
30*4882a593Smuzhiyun          - const: mediatek,mt2701-smi-larb
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  reg:
33*4882a593Smuzhiyun    maxItems: 1
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  clocks:
36*4882a593Smuzhiyun    description: |
37*4882a593Smuzhiyun      apb and smi are mandatory. gals(global async local sync) is optional.
38*4882a593Smuzhiyun    minItems: 2
39*4882a593Smuzhiyun    maxItems: 3
40*4882a593Smuzhiyun    items:
41*4882a593Smuzhiyun      - description: apb is Advanced Peripheral Bus clock, It's the clock for
42*4882a593Smuzhiyun          setting the register.
43*4882a593Smuzhiyun      - description: smi is the clock for transfer data and command.
44*4882a593Smuzhiyun      - description: the clock for gals.
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  clock-names:
47*4882a593Smuzhiyun    minItems: 2
48*4882a593Smuzhiyun    maxItems: 3
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  power-domains:
51*4882a593Smuzhiyun    maxItems: 1
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  mediatek,smi:
54*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle-array
55*4882a593Smuzhiyun    description: a phandle to the smi_common node.
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun  mediatek,larb-id:
58*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
59*4882a593Smuzhiyun    minimum: 0
60*4882a593Smuzhiyun    maximum: 31
61*4882a593Smuzhiyun    description: the hardware id of this larb. It's only required when this
62*4882a593Smuzhiyun      hardward id is not consecutive from its M4U point of view.
63*4882a593Smuzhiyun
64*4882a593Smuzhiyunrequired:
65*4882a593Smuzhiyun  - compatible
66*4882a593Smuzhiyun  - reg
67*4882a593Smuzhiyun  - clocks
68*4882a593Smuzhiyun  - clock-names
69*4882a593Smuzhiyun  - power-domains
70*4882a593Smuzhiyun
71*4882a593SmuzhiyunallOf:
72*4882a593Smuzhiyun  - if:  # HW has gals
73*4882a593Smuzhiyun      properties:
74*4882a593Smuzhiyun        compatible:
75*4882a593Smuzhiyun          enum:
76*4882a593Smuzhiyun            - mediatek,mt8183-smi-larb
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun    then:
79*4882a593Smuzhiyun      properties:
80*4882a593Smuzhiyun        clocks:
81*4882a593Smuzhiyun          minItems: 2
82*4882a593Smuzhiyun          maxItems: 3
83*4882a593Smuzhiyun        clock-names:
84*4882a593Smuzhiyun          minItems: 2
85*4882a593Smuzhiyun          items:
86*4882a593Smuzhiyun            - const: apb
87*4882a593Smuzhiyun            - const: smi
88*4882a593Smuzhiyun            - const: gals
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun    else:
91*4882a593Smuzhiyun      properties:
92*4882a593Smuzhiyun        clocks:
93*4882a593Smuzhiyun          minItems: 2
94*4882a593Smuzhiyun          maxItems: 2
95*4882a593Smuzhiyun        clock-names:
96*4882a593Smuzhiyun          items:
97*4882a593Smuzhiyun            - const: apb
98*4882a593Smuzhiyun            - const: smi
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun  - if:
101*4882a593Smuzhiyun      properties:
102*4882a593Smuzhiyun        compatible:
103*4882a593Smuzhiyun          contains:
104*4882a593Smuzhiyun            enum:
105*4882a593Smuzhiyun              - mediatek,mt2701-smi-larb
106*4882a593Smuzhiyun              - mediatek,mt2712-smi-larb
107*4882a593Smuzhiyun              - mediatek,mt6779-smi-larb
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun    then:
110*4882a593Smuzhiyun      required:
111*4882a593Smuzhiyun        - mediatek,larb-id
112*4882a593Smuzhiyun
113*4882a593SmuzhiyunadditionalProperties: false
114*4882a593Smuzhiyun
115*4882a593Smuzhiyunexamples:
116*4882a593Smuzhiyun  - |+
117*4882a593Smuzhiyun    #include <dt-bindings/clock/mt8173-clk.h>
118*4882a593Smuzhiyun    #include <dt-bindings/power/mt8173-power.h>
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun    larb1: larb@16010000 {
121*4882a593Smuzhiyun      compatible = "mediatek,mt8173-smi-larb";
122*4882a593Smuzhiyun      reg = <0x16010000 0x1000>;
123*4882a593Smuzhiyun      mediatek,smi = <&smi_common>;
124*4882a593Smuzhiyun      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
125*4882a593Smuzhiyun      clocks = <&vdecsys CLK_VDEC_CKEN>,
126*4882a593Smuzhiyun               <&vdecsys CLK_VDEC_LARB_CKEN>;
127*4882a593Smuzhiyun      clock-names = "apb", "smi";
128*4882a593Smuzhiyun    };
129