1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale Multi Mode DDR controller (MMDC) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <Anson.Huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun oneOf: 15*4882a593Smuzhiyun - const: fsl,imx6q-mmdc 16*4882a593Smuzhiyun - items: 17*4882a593Smuzhiyun - enum: 18*4882a593Smuzhiyun - fsl,imx6qp-mmdc 19*4882a593Smuzhiyun - fsl,imx6sl-mmdc 20*4882a593Smuzhiyun - fsl,imx6sll-mmdc 21*4882a593Smuzhiyun - fsl,imx6sx-mmdc 22*4882a593Smuzhiyun - fsl,imx6ul-mmdc 23*4882a593Smuzhiyun - fsl,imx7ulp-mmdc 24*4882a593Smuzhiyun - const: fsl,imx6q-mmdc 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun reg: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clocks: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunrequired: 33*4882a593Smuzhiyun - compatible 34*4882a593Smuzhiyun - reg 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunadditionalProperties: false 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunexamples: 39*4882a593Smuzhiyun - | 40*4882a593Smuzhiyun #include <dt-bindings/clock/imx6qdl-clock.h> 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun memory-controller@21b0000 { 43*4882a593Smuzhiyun compatible = "fsl,imx6q-mmdc"; 44*4882a593Smuzhiyun reg = <0x021b0000 0x4000>; 45*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun memory-controller@21b4000 { 49*4882a593Smuzhiyun compatible = "fsl,imx6q-mmdc"; 50*4882a593Smuzhiyun reg = <0x021b4000 0x4000>; 51*4882a593Smuzhiyun }; 52