1*4882a593SmuzhiyunFreescale DDR memory controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunProperties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : Should include "fsl,chip-memory-controller" where 6*4882a593Smuzhiyun chip is the processor (bsc9132, mpc8572 etc.), or 7*4882a593Smuzhiyun "fsl,qoriq-memory-controller". 8*4882a593Smuzhiyun- reg : Address and size of DDR controller registers 9*4882a593Smuzhiyun- interrupts : Error interrupt of DDR controller 10*4882a593Smuzhiyun- little-endian : Specifies little-endian access to registers 11*4882a593Smuzhiyun If omitted, big-endian will be used. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample 1: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun memory-controller@2000 { 16*4882a593Smuzhiyun compatible = "fsl,bsc9132-memory-controller"; 17*4882a593Smuzhiyun reg = <0x2000 0x1000>; 18*4882a593Smuzhiyun interrupts = <16 2 1 8>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample 2: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun ddr1: memory-controller@8000 { 25*4882a593Smuzhiyun compatible = "fsl,qoriq-memory-controller-v4.7", 26*4882a593Smuzhiyun "fsl,qoriq-memory-controller"; 27*4882a593Smuzhiyun reg = <0x8000 0x1000>; 28*4882a593Smuzhiyun interrupts = <16 2 1 23>; 29*4882a593Smuzhiyun }; 30